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28
Architectural Descriptions for FPGA Circuits
 IEEE Computer Society
, 1995
"... FPGAbased synthesis tools require information about behaviour and architectural to make effective use of the limited number of cells typically available. A hardware description language which models layout and behaviour is used to elegantly specify circuit architecture. This source level informatio ..."
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FPGAbased synthesis tools require information about behaviour and architectural to make effective use of the limited number of cells typically available. A hardware description language which models layout and behaviour is used to elegantly specify circuit architecture. This source level information is used to efficiently translate circuit descriptions onto FPGA devices. 1 Introduction FPGAs offer many advantages for many kinds of applications and present new opportunities for system design [DeHon 94], but their main disadvantages are the limited number of cells available on a single chip and the difficulty of performing global communication. It is important that the available cells are utilized efficiently . One way to do this is to design circuits with a low level schematic editor and manually configure the cells and routing elements. Although this method allows the realization of highly optimised hardware, it has several shortcomings. Design at the gate level is error prone, and c...
A Methodology for the Formal Verification of FFT Algorithms in HOL
 In Formal Methods in ComputerAided Design, LNCS 3312
, 2004
"... Abstract. This paper addresses the formal specification and verification of fast Fourier transform (FFT) algorithms at different abstraction levels based on the HOL theorem prover. We make use of existing theories in HOL on real and complex numbers, IEEE standard floatingpoint, and fixedpoint ar ..."
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Abstract. This paper addresses the formal specification and verification of fast Fourier transform (FFT) algorithms at different abstraction levels based on the HOL theorem prover. We make use of existing theories in HOL on real and complex numbers, IEEE standard floatingpoint, and fixedpoint arithmetics to model the FFT algorithms. Then, we derive, by proving theorems in HOL, expressions for the accumulation of roundoff error in floating and fixedpoint FFT designs with respect to the corresponding ideal real and complex numbers specification. The HOL formalization and proofs are found to be in good agreement with the theoretical paperandpencil counterparts. Finally, we use a classical hierarchical proof approach in HOL to prove that the FFT implementations at the register transfer level (RTL) implies the corresponding high level fixedpoint algorithmic specification. 1
Proving existential theorems when importing results from MDG to HOL
 TPHOLS 2001 SUPPLEMENTAL PROCEEDINGS, INFORMATIC RESEARCH REPORT EDIINFRR0046
, 2001
"... An existential theorem, for the specification or implementation of hardware, states that for any inputs there must exist at least one output which is consistent with it. It is proved to prevent an inconsistent model being produced and it is required to formally import the verification result from on ..."
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An existential theorem, for the specification or implementation of hardware, states that for any inputs there must exist at least one output which is consistent with it. It is proved to prevent an inconsistent model being produced and it is required to formally import the verification result from one verification system to another system. In this paper, we investigate the verification of the existential theorems of hardware specifications and implementations. Whilst much of the approach is generally applicable, we specifically consider a hybrid system linking the MDG hardware verification system with the HOL interactive proof system. We investigate existential theorems based on the syntax and semantics of the MDG input language (MDGHDL) in HOL. We define an output representation for each component in the MDGHDL component library. We summarize a general method which is used to prove the existential theorem for any MDGHDL program. The method can also be used to solve other existentially quantified goals.
Providing a Formal Linkage between MDG and HOL
, 2002
"... We describe an approach for formally verifying the linkage between a symbolic state enumeration system and a theorem proving system. This involves the following three stages of proof. Firstly we prove theorems about the correctness of the translation part of the symbolic state system. It interface ..."
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We describe an approach for formally verifying the linkage between a symbolic state enumeration system and a theorem proving system. This involves the following three stages of proof. Firstly we prove theorems about the correctness of the translation part of the symbolic state system. It interfaces between low level decision diagrams and high level description languages. We ensure that the semantics of a program is preserved in those of its translated form. Secondly we prove linkage theorems: theorems that justify introducing a result from a state enumeration system into a proof system. Finally we combine the translator correctness and linkage theorems. The resulting new linkage theorems convert results to a high level language from the low level decision diagrams that the result was actually proved about in the state enumeration system.They justify importing lowlevel external verification results into a theorem prover. We use a linkage between the HOL system and a simplified version of the MDG system to illustrate the ideas and consider a small example that integrates two applications from MDG and HOL to illustrate the linkage theorems.
An Approach for the Formal Verification of DSP Designs using Theorem Proving
"... In this paper we propose a framework for the incorporation of formal methods in the design flow of DSP (Digital Signal Processing) systems in a rigorous way. In the proposed approach we model and verify DSP descriptions at different abstraction levels using higherorder logic based on the HOL theore ..."
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In this paper we propose a framework for the incorporation of formal methods in the design flow of DSP (Digital Signal Processing) systems in a rigorous way. In the proposed approach we model and verify DSP descriptions at different abstraction levels using higherorder logic based on the HOL theorem prover. This framework enables the formal verification of DSP designs which in the past could only be done partially using conventional simulation techniques. To this end, we provide a shallow embedding of DSP descriptions in HOL at the floatingpoint, fixedpoint, behavioral, RTL, and netlist gate levels. We make use of existing formalization of floatingpoint theory in HOL and a parallel one developed for fixedpoint arithmetic. The high ability of abstraction in HOL allows a seamless hierarchical verification encompassing the whole DSP design path, starting from top level floating and fixedpoint algorithmic descriptions down to RTL, and gate level implementations. We illustrate the new verification framework on FFT algorithm as case study. I.
A Hierarchical Verification of The IEEE754 TableDriven Floating Point Exponential Function using HOL
, 2001
"... ..."
Hierarchical verification of the implementation of the ieee754 tabledriven floatingpoint exponential function using hol
 In International Conference on Theorem Proving in HigherOrder Logics (TPHOLs’01
, 2001
"... Abstract. The IEEE754 floatingpoint standard is considered one of the most important standards, and is used in nearly all floatingpoint applications. In this paper, we have formalized and verified a hardware implementation of the TableDriven algorithm for the floatingpoint exponential function. ..."
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Abstract. The IEEE754 floatingpoint standard is considered one of the most important standards, and is used in nearly all floatingpoint applications. In this paper, we have formalized and verified a hardware implementation of the TableDriven algorithm for the floatingpoint exponential function. Throughout this paper, we have used a hierarchical approach in formally modeling and verifying in HOL the floatingpoint exponential function from the gate level implementation up to a behavioral specification written by Harrison [7]. 1
The Semantics of TLA on the PVS Theorem Prover
, 1996
"... An implementation of Lamport's Temporal Logic of Actions (TLA) on a higher order logic theorem prover is described. TLA is a temporal logic, for which a syntax and semantics are defined, based on an action logic which is represented by higher order functions. The temporal logic includes quantif ..."
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An implementation of Lamport's Temporal Logic of Actions (TLA) on a higher order logic theorem prover is described. TLA is a temporal logic, for which a syntax and semantics are defined, based on an action logic which is represented by higher order functions. The temporal logic includes quantifiers for variables with constant values and for variables whose values change over time. The semantics of the latter depend on an auxiliary function which cannot be defined by primitive recursion and an alternative is given based on the Hilbert ffl operator. 1 Introduction The Temporal Logic of Actions (Lamport, 1994) is a system for reasoning about programs by considering the changes made to program variables during an execution. Actions are boolean expressions relating the values of the variables before and after some event, typically the execution of a command, of the program. Propositional operators are defined on actions giving the base of the temporal logic (the modal system S4.3.1, see Ab...
A MONAbased Decision Procedure for Propositional Interval Temporal Logic
, 2003
"... Interval Temporal Logic (ITL) is a finitetime linear temporal logic with applications in hardware verification, temporal logic programming and specification of multimedia documents. Due to the inherently nonelementary complexity of its decision problem, e#cient ITLbased verification tools have b ..."
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Interval Temporal Logic (ITL) is a finitetime linear temporal logic with applications in hardware verification, temporal logic programming and specification of multimedia documents. Due to the inherently nonelementary complexity of its decision problem, e#cient ITLbased verification tools have been di#cult to develop.
The Application of Formal Verification to SPW Designs
 In Proceedings Euromicro Symposium on Digital System Design, IEEE Computer
, 2003
"... The Signal Processing WorkSystem (SPW) of Cadence is an integrated framework for developing DSP and communications products. Formal verification is a complementary technique to simulation based on mathematical logic. The HOL system is an environment for interactive theorem proving in a higherorder ..."
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The Signal Processing WorkSystem (SPW) of Cadence is an integrated framework for developing DSP and communications products. Formal verification is a complementary technique to simulation based on mathematical logic. The HOL system is an environment for interactive theorem proving in a higherorder logic. It has an open userextensible architecture which makes it suitable for providing proof support for embedded languages. In this paper, we propose an approach to model SPW descriptions at different abstraction levels in HOL based on the shallow embedding technique. This will enable the formal verification of SPW designs which in the past could only be verified partially using conventional simulation techniques. We illustrate this novel application through a simple case study of a Notch filter.