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Alexandria: Libraries of abstract, verified hardware modules
 In 2nd Workshop on Libraries, Component Modeling, and Quality Assurance
, 1997
"... Abstract Individual pieces to support hierarchical verification have existed for several years but have not been integrated into one tool. The tool for creating abstract libraries described in this paper ties the various techniques into one package designed to support hierarchical verification among ..."
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Abstract Individual pieces to support hierarchical verification have existed for several years but have not been integrated into one tool. The tool for creating abstract libraries described in this paper ties the various techniques into one package designed to support hierarchical verification among collaborating researchers. In these libraries, predicate types organize specification information, abstract theories model modular components and public key encryption increases the trustworthiness of externally proven theorems. A prototype tool for creating libraries called Alexandria has been implemented in the HOL90 proof assistant for use with the BOLT HDL using PGP encryption to sign verified theorems. 1 Introduction Useful hardware modules are complex and often designed by teams using existing components. Hardware verification on the other hand is typically performed by one person making no use of preverified moduleseven if other modules exist. Hierarchical verification of largescale designs is impeded by several obstacles:
Supporting Reasoning about Functional Programs: An Operational Approach
 In Glasgow Workshop on Functional Programming
, 1995
"... ©Copyright in this paper belongs to the author(s) Published in collaboration with the ..."
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©Copyright in this paper belongs to the author(s) Published in collaboration with the
A Tool to Support Formal Reasoning about Computer Languages
 Proceedings of the Third International Workshop on Tools and Algorithms for the Construction and Analysis of Systems (TACAS'97), volume 1217 of Lecture Notes in Computer Science
, 1997
"... . A tool to support formal reasoning about computer languages and specific language texts is described. The intention is to provide a tool that can build a formal reasoning system in a mechanical theorem prover from two specifications, one for the syntax of the language and one for the semantics ..."
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. A tool to support formal reasoning about computer languages and specific language texts is described. The intention is to provide a tool that can build a formal reasoning system in a mechanical theorem prover from two specifications, one for the syntax of the language and one for the semantics. A parser, prettyprinter and internal representations are generated from the former. Logical representations of syntax and semantics, and associated theorem proving tools, are generated from the combination of the two specifications. The main aim is to eliminate tedious work from the task of prototyping a reasoning tool for a computer language, but the abstract specifications of the language also assist the automation of proof. 1 Introduction For several decades theorem proving systems have been used to reason about computer languages. A common approach has been to define the semantics of a language in the logic of the theorem prover. This may be done by defining new constants in t...
A Methodology for the Formal Verification of FFT Algorithms in HOL
 In Formal Methods in ComputerAided Design, LNCS 3312
, 2004
"... Abstract. This paper addresses the formal specification and verification of fast Fourier transform (FFT) algorithms at different abstraction levels based on the HOL theorem prover. We make use of existing theories in HOL on real and complex numbers, IEEE standard floatingpoint, and fixedpoint ar ..."
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Abstract. This paper addresses the formal specification and verification of fast Fourier transform (FFT) algorithms at different abstraction levels based on the HOL theorem prover. We make use of existing theories in HOL on real and complex numbers, IEEE standard floatingpoint, and fixedpoint arithmetics to model the FFT algorithms. Then, we derive, by proving theorems in HOL, expressions for the accumulation of roundoff error in floating and fixedpoint FFT designs with respect to the corresponding ideal real and complex numbers specification. The HOL formalization and proofs are found to be in good agreement with the theoretical paperandpencil counterparts. Finally, we use a classical hierarchical proof approach in HOL to prove that the FFT implementations at the register transfer level (RTL) implies the corresponding high level fixedpoint algorithmic specification. 1
An Embedding of Ruby in Isabelle
 In McRobbie, Slaney [23
, 1996
"... . This paper describes a semantical embedding of the relation based language Ruby in ZermeloFraenkel set theory (ZF) using the Isabelle theorem prover. A small subset of Ruby, called Pure Ruby, is embedded as a conservative extension of ZF and many useful structures used in connection with VLSI ..."
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. This paper describes a semantical embedding of the relation based language Ruby in ZermeloFraenkel set theory (ZF) using the Isabelle theorem prover. A small subset of Ruby, called Pure Ruby, is embedded as a conservative extension of ZF and many useful structures used in connection with VLSI design are defined in terms of Pure Ruby. The inductive package of Isabelle is used to characterise the Pure Ruby subset to allow proofs to be performed by structural induction over the Pure Ruby elements. 1 Introduction Ruby [5] is a relation based language intended for specifying VLSI circuits. A circuit is described by a binary relation between appropriate, possibly complex domains of values, and simple relations can be combined into more complex relations by a variety of combining forms. The Ruby relations generate an algebra which defines a set of equivalences. These are used in the Ruby design process which typically involves a transformation from a "specification" to an "impleme...
Providing a Formal Linkage between MDG and HOL
, 2002
"... We describe an approach for formally verifying the linkage between a symbolic state enumeration system and a theorem proving system. This involves the following three stages of proof. Firstly we prove theorems about the correctness of the translation part of the symbolic state system. It interface ..."
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We describe an approach for formally verifying the linkage between a symbolic state enumeration system and a theorem proving system. This involves the following three stages of proof. Firstly we prove theorems about the correctness of the translation part of the symbolic state system. It interfaces between low level decision diagrams and high level description languages. We ensure that the semantics of a program is preserved in those of its translated form. Secondly we prove linkage theorems: theorems that justify introducing a result from a state enumeration system into a proof system. Finally we combine the translator correctness and linkage theorems. The resulting new linkage theorems convert results to a high level language from the low level decision diagrams that the result was actually proved about in the state enumeration system.They justify importing lowlevel external verification results into a theorem prover. We use a linkage between the HOL system and a simplified version of the MDG system to illustrate the ideas and consider a small example that integrates two applications from MDG and HOL to illustrate the linkage theorems.
Representing WP Semantics in Isabelle/ZF
 TPHOLs: The 12th International Conference on Theorem Proving in HigherOrder Logics, number 1690 in lncs
, 1999
"... . We present a shallow embedding of the weakest precondition semantics for a program renement language. We use the Isabelle/ZF theorem prover for untyped set theory, and statements in our renement language are represented as set transformers. Our representation is signi cant in making use of the ..."
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. We present a shallow embedding of the weakest precondition semantics for a program renement language. We use the Isabelle/ZF theorem prover for untyped set theory, and statements in our renement language are represented as set transformers. Our representation is signi cant in making use of the expressiveness of Isabelle/ZF's set theory to represent states as dependentlytyped functions from variable names to their values. This lets us give a uniform treatment of statements such as variable assignment, framed specication statements, local blocks, and parameterisation. ZF set theory requires set comprehensions to be explicitly bounded. This requirement propagates to the denitions of statements in our renement language, which have operands for the state type. We reduce the syntactic burden of repeatedly writing the state type by using Isabelle's metalogic to dene a lifted set transformer language which implicitly passes the state type to statements. Weakest precondi...
Formally Analysed Dynamic Synthesis of Hardware
 in Theorem Proving in Higher Order Logics: Emerging Trends: 11th International Conference (TPHOLs'98
, 2001
"... . Dynamic hardware reconfiguration based on runtime system specialization is viable with Xilinx XC6200 series FPGAs. The research challenge for formal verification is to help ensure the correctness of dynamically generated hardware. In this paper, the approach is to verify a specialization synthesi ..."
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. Dynamic hardware reconfiguration based on runtime system specialization is viable with Xilinx XC6200 series FPGAs. The research challenge for formal verification is to help ensure the correctness of dynamically generated hardware. In this paper, the approach is to verify a specialization synthesis algorithm used to reconfigure FPGA designs. The verification approach is based on a deep embedding of a language for netlists and the relational hardware modeling style. 1 Introduction Most microelectronic circuit design is done as ASIC design. The design is validated extensively, either by simulation or by formal verification methods, before it is manufactured. The production of the design as a chip will take several months before the designer can test the hardware itself. If the system fails to satisfy the functional specification at the testing stage, the designers must redesign the circuit and redo the whole validation, production, and test cycle. The flexibility of implementing a ...
Stronglytyped Theory of Structures And Behaviours
 Correct Hardware Design and Verification Methods, Lecture Notes In Computer Science
, 1993
"... This paper describes an approach to capturing the relation between circuits and their behaviours within a formal theory. The method exploits dependent types to achieve a rigorous yet theoretically simple connection between circuits (treated as graphs) and their behavioural specifications (treate ..."
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This paper describes an approach to capturing the relation between circuits and their behaviours within a formal theory. The method exploits dependent types to achieve a rigorous yet theoretically simple connection between circuits (treated as graphs) and their behavioural specifications (treated as predicates). An example is given of a behavioural extraction function and it is shown how a type for modules can be defined that is sufficiently fine to guarantee that the behaviour of a module will satisfy its behavioural specification. The method is discussed in relation to VHDL and in relation to formal synthesis, (a process whereby one starts with a behavioural specification and, using an interactive goaldirected approach, ends up with a circuit and a formal proof that it satisfies the given behavioural specification).