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220
Test Set Compaction Algorithms for Combinational Circuits
, 2000
"... This paper presents a new algorithm, Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under the single stuckat fault model, and a new heuristic for estimating the minimum single stuckat fault test set size. These algorithms together with the dynamic co ..."
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Cited by 116 (5 self)
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This paper presents a new algorithm, Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under the single stuckat fault model, and a new heuristic for estimating the minimum single stuckat fault test set size. These algorithms together with the dynamic compaction algorithm are incorporated into an advanced ATPG system for combinational circuits, called MinTest. MinTest found better lower bounds and generated smaller test sets than the previously published results for the ISCAS85 and full scan versions of the ISCAS89 benchmark circuits. Keywords test set compaction, minimum test set size estimation, test generation, combinational circuits, stuckat fault model. 2 Footnotes I. Hamzaoglu was with Center for Reliable & HighPerformance Computing, University of Illinois, Urbana, IL 61801. He is now with Motorola Labs, 1301 E. Algonquin Road, Schaumburg, IL 60196. J. H. Patel is with Center for Reliable & HighPerformance Computing, Univers...
Performance optimization of VLSI interconnect layout
 Integration, the VLSI Journal
, 1996
"... This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. ..."
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Cited by 103 (32 self)
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This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, nontree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.
Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors
 Journal of Symbolic Computation
, 2001
"... We compare SATcheckers and decision diagrams on the evaluation of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors. We identify one SATchecker that significantly outperforms the rest. We evaluate ways to enhance its per ..."
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Cited by 87 (12 self)
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We compare SATcheckers and decision diagrams on the evaluation of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors. We identify one SATchecker that significantly outperforms the rest. We evaluate ways to enhance its performance by variations in the generation of the Boolean correctness formulas. We reassess optimizations previously used to speed up the formal verification and probe future challenges.
Reducing Test Application Time for Full Scan Embedded Cores
 IN FTCS
, 1999
"... We propose a new design for testability technique, Parallel Serial Full Scan (PSFS), for reducing the test application time for full scan embedded cores. Test application time reduction is achieved by dividing the scan chain into multiple partitions and shifting in the same vector to each scan chain ..."
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Cited by 75 (2 self)
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We propose a new design for testability technique, Parallel Serial Full Scan (PSFS), for reducing the test application time for full scan embedded cores. Test application time reduction is achieved by dividing the scan chain into multiple partitions and shifting in the same vector to each scan chain through a single scan in input. The experimental results for the ISCAS89 circuits showed that PSFS technique significantly reduces both the test application time and the amount of test data for full scan embedded cores.
Test Vector Decompression via Cyclical Scan Chains and Its Application to Testing CoreBased Designs
 Proc. Int. Test Conf
, 1998
"... A novel test vector compression/decompression technique is proposed for reducing the amount of test data that must be stored on a tester and transferred to each core when testing a corebased design. A small amount of onchip circuitry is used to reduce both the test storage and test time required f ..."
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Cited by 69 (10 self)
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A novel test vector compression/decompression technique is proposed for reducing the amount of test data that must be stored on a tester and transferred to each core when testing a corebased design. A small amount of onchip circuitry is used to reduce both the test storage and test time required for testing a corebased design. The fully specified test vectors provided by the core vendor are stored in compressed form in the tester memory and transferred to the chip where they are decompressed and applied to the core (the compression is lossless). Instead of having to transfer each entire test vector from the tester to the core, a smaller amount of compressed data is transferred instead. This reduces the amount of test data that must be stored on the tester and hence reduces the total amount of test time required for transferring the data with a given test data bandwidth. 1. Introduction Testing systemsonachip containing multiple cores is a major challenge due to limited test acc...
Markovian Analysis of Large Finite State Machines
 IEEE Transactions on CAD
, 1996
"... Regarding finite state machines as Markov chains facilitates the application of probabilistic methods to very large logic synthesis and formal verification problems. In this paper we present symbolic algorithms to compute the steadystate probabilities for very large finite state machines (up to 10 ..."
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Cited by 66 (7 self)
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Regarding finite state machines as Markov chains facilitates the application of probabilistic methods to very large logic synthesis and formal verification problems. In this paper we present symbolic algorithms to compute the steadystate probabilities for very large finite state machines (up to 10 27 states). These algorithms, based on Algebraic Decision Diagrams (ADDs)  an extension of BDDs that allows arbitrary values to be associated with the terminal nodes of the diagrams  determine the steadystate probabilities by regarding finite state machines as homogeneous, discreteparameter Markov chains with finite state spaces, and by solving the corresponding ChapmanKolmogorov equations. We first consider finite state machines with state graphs composed of a single terminal strongly connected component; for this type of systems we have implemented two solution techniques: One is based on the GaussJacobi iteration, the other one is based on simple matrix multiplication. Then we...
Sequential Circuit Test Generation in a Genetic Algorithm Framework
 Proc. Design Automation Conf
, 1994
"... Test generation using deterministic faultoriented algorithms is highly complex and timeconsuming. New approaches are needed to augment the existing techniques, both to reduce execution time and to improve fault coverage. In this work, we describe a genetic algorithm (GA) framework for sequential ci ..."
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Cited by 62 (16 self)
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Test generation using deterministic faultoriented algorithms is highly complex and timeconsuming. New approaches are needed to augment the existing techniques, both to reduce execution time and to improve fault coverage. In this work, we describe a genetic algorithm (GA) framework for sequential circuit test generation. The GA evolves candidate test vectors and sequences, using a fault simulator to compute the fitness of each candidate test. Various GA parameters are studied, including alphabet size, fitness function, generation gap, population size, and mutation rate, as well as selection and crossover schemes. High fault coverages were obtained for most of the ISCAS89 sequential benchmark circuits, and execution times were significantly lower than in a deterministic test generator in most cases. I Introduction Simulationbased test generation has been used to avoid the long execution times of deterministic algorithms and to reduce the complexity of the test generator. In particula...
Synthesis Of Mapping Logic For Generating Transformed PseudoRandom Patterns For Bist
 Proc. of International Test Conference
, 1995
"... During builtin selftest (BIST), the set of patterns generated by a pseudorandom pattern generator may not provide a sufficiently high fault coverage. This paper presents a new technique for synthesizing combinational mapping logic to transform the set of patterns that are generated. The goal is t ..."
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Cited by 51 (16 self)
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During builtin selftest (BIST), the set of patterns generated by a pseudorandom pattern generator may not provide a sufficiently high fault coverage. This paper presents a new technique for synthesizing combinational mapping logic to transform the set of patterns that are generated. The goal is to satisfy test length and fault coverage requirements while minimizing area overhead. For a given pseudorandom pattern generator and circuit under test, there are many possible mapping functions that will provide a desired fault coverage for a given test length. This paper formulates the problem of finding a mapping function that can be implemented with a small number of gates as a one of finding a minimum rectangle cover in a binate matrix. A procedure is described for selecting a mapping function and synthesizing mapping logic to implement it. Experimental results for the procedure are compared with published results for other methods. It is shown that by performing iterative global opera...
A Set of Benchmarks for Modular Testing of SOCs
 ITC'02
, 2002
"... This paper presents the ITC'02 SOC Test Benchmarks. The purpose of this new benchmark set is to stimulate research into new methods and tools for modular testing of SOCs and to enable the objective comparison of such methods and tools with respect to effectiveness and efficiency. The paper defines ..."
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Cited by 51 (19 self)
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This paper presents the ITC'02 SOC Test Benchmarks. The purpose of this new benchmark set is to stimulate research into new methods and tools for modular testing of SOCs and to enable the objective comparison of such methods and tools with respect to effectiveness and efficiency. The paper defines the benchmark format and naming scheme, and presents the benchmark SOCs. In addition, it provides an overview of the research problems that can be addressed and evaluated by means of this benchmark set. These research problems include the design of optimized test access infrastructures and test schedules.
Test Scheduling for CoreBased Systems Using MixedInteger Linear Programming
, 2000
"... We present optimal solutions to the test scheduling problem for corebased systems. Given a set of tasks (test sets for the cores), a set of test resources (e.g., test buses, BIST hardware) and a test access architecture, we determine start times for the tasks such that the total test application ti ..."
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Cited by 46 (8 self)
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We present optimal solutions to the test scheduling problem for corebased systems. Given a set of tasks (test sets for the cores), a set of test resources (e.g., test buses, BIST hardware) and a test access architecture, we determine start times for the tasks such that the total test application time is minimized. We show that the test scheduling decision problem is equivalent to theprocessor open shop scheduling problem and is therefore NPcomplete. However, a commonly encountered instance of this problem ( =2) can be solved in polynomial time. For the general case ( 2), we present a mixedinteger linear programming (MILP) model for optimal scheduling and apply it to a representative corebased system using an MILP solver available in the public domain. We also extend the MILP model to allow optimal test set selection from a set of alternatives. Finally, we present an efficient heuristic algorithm for handling larger systems for which the MILP model may be infeasible. Index Ter...