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Testable Path Delay Fault Cover for Sequential Circuits
, 1996
"... We present an algorithm for identifying a set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently affect the performance of the circuit or no test can be generated for them. To find such faults, our methodology takes advantag ..."
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Cited by 13 (6 self)
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We present an algorithm for identifying a set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently affect the performance of the circuit or no test can be generated for them. To find such faults, our methodology takes advantage of the sequential behavior of the circuit as well as of the information about uncontrollable signals in the sequential circuit. It can handle sequential circuits described as two or multilevel netlists. The outcome of applying our methodology is smaller fault set and possibly smaller test set. We present experimental results on several ISCAS 89 benchmark circuits demonstrating that a large number of path delay faults in these circuits either cannot or does not have to be examined for delay defects.
Identifying Sequentially Untestable Faults Using Illegal States
 In Proc. of the VLSI Test Symposium
, 1995
"... This paper addresses the problem of identifying untestable faults in synchronous sequential circuits without assuming a global reset mechanism. First, we present an efficient algorithm to identify illegal states in the circuit. An important feature of this algorithm is its functional partitioning, w ..."
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Cited by 12 (1 self)
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This paper addresses the problem of identifying untestable faults in synchronous sequential circuits without assuming a global reset mechanism. First, we present an efficient algorithm to identify illegal states in the circuit. An important feature of this algorithm is its functional partitioning, which results in efficient processing of large circuits. The algorithm incrementally builds the set of illegal states which allows it to obtain partial solutions in situations when the search must be curtailed due to resource limitations. No illegal states will be found in such situations by the forward search used in previous methods. Next, we present an algorithm that uses these illegal states to find sequentially untestable faults without exhaustive search. This is unlike all previous methods that rely on automatic test pattern generation (ATPG), which results in very large computational requirements. Our experimental results on benchmark circuits indicate that we find a large number of un...
Redundancy Identification Using Transitive Closure
 in Proc. of the 5th Asian Test Symp
, 1996
"... We analyze all signals of a combinational circuit simultaneously for redundancy. The state of a signal is represented by two binary variables. The first variable is the logic value of the signal. The second variable is the observability status of the signal with respect to all primary outputs. Boole ..."
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Cited by 11 (5 self)
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We analyze all signals of a combinational circuit simultaneously for redundancy. The state of a signal is represented by two binary variables. The first variable is the logic value of the signal. The second variable is the observability status of the signal with respect to all primary outputs. Boolean equations specify local relationships of these variables in a manner similar to the neural network or Boolean satisfiability method. All pairwise terms appearing in these Boolean equations are used to construct an implication graph, for which the transitive closure graph is obtained. Any signal assignments or relations found from the transitive closure are substituted into higherorder terms of the Boolean equations, some of which reduce to pairwise terms. Such cases are iteratively included in the transitive closure until no more reductions are possible. In the final transitive closure, all signals are examined for the following conditions of redundancy: (1) If a signal and its complement imply each other (contradiction) then both stuckat faults on that signal are redundant; (2) If one value implies the other value (fixation) then one of the stuckat faults on that signal is redundant; (3) If the true observability status of a signal implies its own false observability status, then both stuckat faults of that signal are redundant; (4) If a certain value of a signal implies the false observability status, then the corresponding stuckat fault is redundant. Despite the apparent similarities with the transitive closure based ATPG, the present method is quite different. Here transitive closure is computed just once, and not recomputed or updated separately for each fault as required in ATPG. We give ISCAS '85 benchmark results. For c6288, we could identify 31 out of 33 redu...
Fast Identification of Untestable Delay Faults Using Implications
 In Proceedings IEEE International Conference on ComputerAided Design
, 1997
"... We propose a novel algorithm to rapidly identify untestable delay faults using precomputed static logic implications. Our faultindependent analysis identifies large sets of untestable faults, if any, without enumerating them. The cardinalities of these sets are obtained by using a counting algorit ..."
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Cited by 9 (0 self)
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We propose a novel algorithm to rapidly identify untestable delay faults using precomputed static logic implications. Our faultindependent analysis identifies large sets of untestable faults, if any, without enumerating them. The cardinalities of these sets are obtained by using a counting algorithm that has quadratic complexity in the number of lines. Since our method is based on an incomplete set of logic implications, it gives only a lower bound on the number of untestable faults. A postprocessing step can list the untestable faults, if desired. Targeting untestable delay faults for test generation by an automatic test pattern generation (ATPG) tool can be avoided. The method works for the segment delay fault model and its special case, the path delay fault model, and identifies robustly untestable, nonrobustly untestable, and functionally unsensitizable delay faults. Results on benchmark circuits show that many delay faults are identified as untestable in a very short time. For ...
Untestable Fault Identification Using Recurrence Relations and Impossible Value Assignments
 of Proc. Of Intl conference on VLSI Design
, 2004
"... This paper presents two novel and low cost techniques that can be used for the purpose of untestable fault identification. First, we present a new theorem and a practical method using static implications to identify unexcitable nets using recurrence relations in sequential circuits. Since each unexc ..."
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Cited by 2 (2 self)
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This paper presents two novel and low cost techniques that can be used for the purpose of untestable fault identification. First, we present a new theorem and a practical method using static implications to identify unexcitable nets using recurrence relations in sequential circuits. Since each unexcitable net generally infers to more than one untestable fault, this theorem helps us to quickly identify significantly more sequentially untestable faults. In addition to discovering unexcitable nets using recurrence relations, we propose a second approach that aims at quickly identifying nontrivial multiplenode conflicts, which can then be used to identify additional untestable faults in both combinational and sequential circuits. Unlike previous techniques that concentrate on identifying local conflicts in the circuit, our approach efficiently extends the conflicting value analysis across multiple levels in the circuit to identify more untestable faults. Application of our techniques to both combinational and sequential benchmark circuits showed that significantly more untestable faults can be identified using the proposed approaches, with low overhead in terms of both memory and execution time. 1.
Surprises in Sequential Redundancy Identification
 In Proceedings of the European Design and Test Conference
, 1996
"... This paper addresses some misconceptions about redundancy in synchronous sequential circuits. We provide examples to illustrate the differences between untestability and redundancy and discuss existing techniques to identify sequential redundancy. We show that some of these methods are based on ..."
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Cited by 1 (0 self)
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This paper addresses some misconceptions about redundancy in synchronous sequential circuits. We provide examples to illustrate the differences between untestability and redundancy and discuss existing techniques to identify sequential redundancy. We show that some of these methods are based on incorrect theoretical results. Specifically, we show that untestable faults in balanced pipeline circuits are not necessarily redundant, and that a constant function (i.e. a signal that is always 0 or 1 after initialization) does not always indicate a redundancy. We also show that adding a global reset mechanism or retiming synchronous circuitry may introduce redundancies. 1. Introduction Unintentional logical redundancies may be introduced in a circuit without the knowledge of the designer. Identifying these redundancies may provide useful feedback for designers, helping them in locating design errors or finding ways to simplify the circuit. Redundancy identification (RID) ca...
Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits
"... We introduce theorems that enable efficient identification of indistinguishable fault pairs in synchronous sequential circuits using an iterative logic array of limited length. These theorems can be used for identifying fault pairs that can be dropped from consideration before diagnostic ATPG starts ..."
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We introduce theorems that enable efficient identification of indistinguishable fault pairs in synchronous sequential circuits using an iterative logic array of limited length. These theorems can be used for identifying fault pairs that can be dropped from consideration before diagnostic ATPG starts, thus improving the efficiency of diagnostic ATPG. Experimental results are presented to demonstrate the effectiveness of the proposed theorems, which allow us to identify almost all the indistinguishable fault pairs in finitestate machine benchmarks.
On Removing Redundant Faults in Synchronous Sequential Circuits
"... We describe a timee cient procedure forremoving sequentially redundant faults from synchronous sequential circuits with synchronizing sequences. We use properties of redundant faults and propose several methods to identify subsets of redundant faults that can be removed simultaneously from the circ ..."
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We describe a timee cient procedure forremoving sequentially redundant faults from synchronous sequential circuits with synchronizing sequences. We use properties of redundant faults and propose several methods to identify subsets of redundant faults that can be removed simultaneously from the circuit. By removing several redundant faults simultaneously, the number of repetitions of the test generation procedure invoked to identify redundant faults is reduced. Experimental results presented in this work demonstrate the e ectiveness of the proposed removal procedure. 1
Cadence Design Systems
"... In this paper, we make two major contributions: First, to enhance Boolean learning, we propose a new class of logic implications called extended forward implications. Usinganovel concept called implicationfrontier, extended forward implications efficiently capture those nontrivial relationships wh ..."
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In this paper, we make two major contributions: First, to enhance Boolean learning, we propose a new class of logic implications called extended forward implications. Usinganovel concept called implicationfrontier, extended forward implications efficiently capture those nontrivial relationships which previous techniques failed to identify. Secondly, we introduce the concept of dual recurrence relations in sequential circuits, and propose a new theorem which uses this concept to quickly identify sequentially untestable faults. Our tool based on the proposed extended forward implications and the new theorem was applied to identify untestable faults in benchmark circuits. Significantly more untestable faults than reported by earlier techniques, low memory overhead and low computational complexity are the noteworthy features of our tool. 1.