. We describe a family of current-mode circuits with multiple inputs and multiple outputs whose output currents are products and/or quotients of powers of the input currents. These circuits are made up of multiple-input floating-gate MOS (FGMOS) transistors operating in the subthreshold regime. The powers are set by capacitor ratios; hence, they can be quite accurate. We analyze the general family of such circuits and present experimental data from several members that we fabricated in a standard 2¯m double-poly p-well process through MOSIS. 1. Introduction Information processing using analog VLSI systems has recently become the subject of much interest and active research [1], [2]. In particular, the current-mode approach is the focus of much attention [3]. In this paradigm, the quantities of interest are represented by currents, whereas the circuit voltages are thought of as playing only an incidental role. Among the vast array of nonlinear operations required to perform current-mod...

In this thesis a new signal processing technique is presented. This technique exploits the use of pulses as the signalling mechanism. This Palmo 1 signalling method applied to signal processing is novel, combining the advantages of both digital and analogue techniques. Pulsed signals are robust, inherently low-power, easily regenerated, and easily distributed across and between chips. The Palmo cells used to perform analogue operations on the pulsed signals are compact, fast, simple and programmable.

The key performance of many analog circuits is directly related to accurate capacitor ratios. It is well known that capacitor ratio precision is greatly enhanced by paralleling identical size unit capacitors in a commoncentroid geometry. In this paper, a general algorithm for fitting arbitrary capacitor ratios in a common-centroid unit-capacitor array is presented. The algorithm gives special care to both non-integer and identical ratios in order to minimize mismatch. A method for capacitance mismatch estimation based upon an oxide gradient model is also introduced. It enables the comparison of different unit-capacitor array assignments. Layout issues are discussed with emphasis on a generic routing model. Both the algorithm and the mismatch estimation method are implemented in an automatic capacitor array generation tool.

As chip complexity explodes and compressed product development cycles relentlessly scale time-tomarket pressures, designers must accomplish more ambitious objectives in less time. For an increasing number of designers, the secret to quickly building highly integrated systems on a chip (SoCs) in a shrinking development cycle lies in the extensive reuse of silicon-proven megafunctions or blocks.

Serietitel och serienummer Title of series, numbering ISSN 1400-3902 URL för elektronisk version

Abstract—Many practical applications require a comparison of the Hamming weights of two N-bit binary vectors. This comparison can be performed in a fully digital manner or by a mix of analog and digital techniques. In this paper, we propose a design in the latter category that exhibits advantages in speed and power dissipation compared with the best previous designs. The proposed design comprises of two switched-capacitor arrays associated with two comparators placed in parallel, collectively providing a complete comparison outcome of “>”, “<”, or “=”. The switched-capacitor array circuit is composed of uniform capacitances, thus associating identical charges with all bits, independent of their positions in the input bit-vectors. Once charge accumulation has occurred based on the asserted inputs, the two comparators release the final decision concurrently. The structure is shown to support wide input vectors on the order of 64 bits, while requiring a small silicon area for capacitor array structures, CMOS switches, and latched comparators to compute and store the comparison outcome. HSPICE simulation shows a total power consumption of 1.136 mW, evaluated at the operating frequency of 1 GHz (based on input-to-decision delay) for 16-bit input vectors under 0.15 µm TSMC technology.