Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or a failure to route all signals. This paper presents PathFinder, a router that balances the goals of performance and routability. PathFinder uses an iterative algorithm that converges to a solution in which all signals are routed while achieving close to the optimal performance allowed by the placement. Routability is achieved by forcing signals to negotiate for a resource and thereby determine which signal needs the resource most. Delay is minimized by allowing the more critical signals a greater say in this negotiation. Because PathFinder requires only a directed graph to describe the architecture of routing resources, it adapts readily to a wide variety of FPGA architectures such as Triptych, Xilinx 3000 and mesh-connected arrays of FPGAs. The results of routing...

Field-programmable gate arrays (FPGAs) are becoming an increasingly important implementation medium for digital logic. One of the most important keys to using FPGAs effectively is a complete, automated software system for mapping onto the FPGA architecture. Unfortunately, many of the tools necessary require different techniques than traditional circuit implementation options, and these techniques are often developed specifically for only a single FPGA architecture. In this paper we describe automatic mapping tools for Triptych, an FPGA architecture with improved logic density and performance over commercial FPGAs. These tools include a simulated-annealing placement algorithm that handles the routability issues of fine-grained FPGAs, and an architecture-adaptive routing algorithm that can easily be retargeted to other FPGAs. We also describe extensions to these algorithms for mapping asynchronous circuits to Montage, the first FPGA architecture to completely support asyn...

A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow. Examples drawn from industrial applications are reported to illustrate the effectiveness of the approach. Keywords--- Layout, Analog Design, Constraint-Driven Layout. I. Introduction The layout of analog circuits is intrinsically more difficult than the d...

In this paper, we address the routability and analog performance issues involved in routing for array-based FPAAs that have single-segment horizontal and vertical routing resources. We then present FAAR (Field-programmable Analog Array Router) and describe a routing algorithm developed for the target array-based FPAA architecture. Sequential routing technique is used for routing multi-terminalnets as well as multiple nets. Multi-terminal nets are broken into two-terminal pairs and routed. We use the notion of resource demand as a measure of the effect of a net-route on the routing of the other nets, while the number of programmable switches and the net-crossings are used as the metrics of interconnect parasitics. We present experiments to study the effect of various parameters such as the number of nets, terminals, CABs and IO cells on the routing as well as the performance degradation. FAAR routes with high efficiency while keeping performance degradation small, and has considerably s...

ence in Electrical and Computer Engineering,, This work was supported by the Semiconductor Research Corporation and IBM. This thesis, presents new results in constraint-directed placement and muting of device-level ar~alog cells. We describe the first algorithm for latchup-aware device placement ’,Hat guarantees sufficient placement of well/substrate,contacts by simultaneous placement of latchup protection geometry and devices. A novel cost-to-target predictor for best-first cost-based maze routing is presented, which is shown to be highly effective in multi-layer multi-terminal routing problems. The predictor and a new scheme for pruning evolving palhs that violate user-supplied parasitic bounds, combine to allow faster, deeper, more optimum and tightly-constrained routing of analog signals in dense placements. Experimental results suggest the strategy avoids the artifacts of crosstalk-for-length trade-offs seen in earlier algorithms, and adlows users more fine-grain

New placement techniques are presented which substantially improve the process of automatic layout generation of analog IC's. Extremely tight specifications can be enforced on high-performance analog circuits by using simultaneous placement and module optimization. An algorithmic approach to module generation provides alternative sets of modules optimized with respect to area and performance but equivalent in terms of parasitics and topology. The final module selection is performed during the placement phase, based on Simulated Annealing. The flexibility of the annealing algorithm has been significantly improved, thus making it possible to more efficiently exploit the tradeoffs between area, parasitics and matching. 1 Introduction Layout design automation of analog IC's has seen considerable improvements in recent years despite a continuous increase of complexity and sophistication of analog and mixed-signal systems. On the one hand, denser and more advanced technologies have led to f...

| This paper addresses the problem of layout design automation of datapath cells. We present a novel approach to transistor placement problem for custom datapath designs and demonstrate that it can be applied to practical designs. Our approach is based on an analytical model which employs a mixed integer linear programming (MILP) technique. The novelty and originality of the method is the ecient management of the complexity of the underlying mathematical model. Our prototype tool automatically handles transistor merging, folding, and intra-cell component sharing. I. Introduction Layout generation for high-performance datapaths has been typically done manually due to stringent requirements imposed on area and performance of such circuits. So far, datapath layout did not enjoy the benets of design automation due to high correlation between quality of layout and circuit performance. However, as the complexity of datapath structures grows the requirement on turnaround time becomes critic...

This paper presents a layout generation tool that aims to reduce the gap between electrical sizing and physical realization of high performance analog circuits. The procedural layout approach is shown to be best suited for this kind of methodologies. Once captured, the procedural description can be used several times to calculate both rapidly and accurately all parasitics that appear during physical realizations without layout generation. Efficient algorithms are developed to take into account analog layout constraints such as matching, parasitic control, shape and reliability considerations. This allows to account for these effects early in the design which guarantees the fulfillment of the required performance specifications, permits to optimize various design aspects in the presence of parasitics and shortens the overall design time by avoiding laborious sizing-layout iterations. An example of a high performance OTA is presented at the end to illustrate the effectiveness of the approach.

This paper describes a new approach to layout compaction of analog integrated circuits which respects all of the performance and technology constraints necessary to guarantee proper analog circuit functionality. Our approach consists of two stages: a fast constraint graph critical path algorithm followed by a general linear programming algorithm. Circuit performance is guaranteed by mapping high-level performance constraints to low-level bounds on parasitics and then to minimum spacing constraints between adjacent nets.

A rigorous and efficient technique is presented for module generation in a maximally stacked layout paradigm for CMOS analog integrated circuits. Analog constraints on symmetry and matching provide a key for heuristics substantially reducing the computational complexity of robust graph algorithms. The solution found minimizes a cost function accounting for parasitic control and routability considerations. Combined with sensitivity analysis and automatic constraint generation, this algorithm provides a suitable performance-driven approach to analog layout module generation. Examples are reported showing the effectiveness of our approach. 1. INTRODUCTION In recent years, several approaches to the automatic synthesis of analog integrated circuits have been proposed [1, 2, 3]. Significant efforts have been made toward a consistent performance-driven methodology [4], such that the respect of high-level specifications is guaranteed in all design stages. However, a severe discontinuity is pr...