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42
Optimal NonUniform WireSizing under the Elmore Delay Model
 in Proc. Int. Conf. on Computer Aided Design
, 1996
"... We consider nonuniform wiresizing for general routing trees under the Elmore delay model. Three minimization objectives are studied: 1) total weighted sinkdelays; 2) total area subject to sinkdelay bounds; and 3) maximum sinkdelay. We first present an algorithm NWSAwd for minimizing total weigh ..."
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Cited by 22 (10 self)
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We consider nonuniform wiresizing for general routing trees under the Elmore delay model. Three minimization objectives are studied: 1) total weighted sinkdelays; 2) total area subject to sinkdelay bounds; and 3) maximum sinkdelay. We first present an algorithm NWSAwd for minimizing total weighted sinkdelays based on iteratively applying the wiresizing formula in [1]. We show that NWSAwd always converges to an optimal wiresizing solution. Based on NWSAwd and the Lagrangian relaxation technique, we obtained two algorithms NWSAdb and NWSAmd which can optimally solve the other two minimization objectives. Experimental results show that our algorithms are efficient both in terms of runtime and storage. For example, NWSAwd, with linear runtime and storage, can solve a 6201wiresegment routingtree problem using about 1.5second runtime and 1.3MB memory on an IBM RS/6000 workstation. 1 Introduction As VLSI technology continues to scale down, interconnect delay has become the d...
An Efficient Approach To Simultaneous Transistor And Interconnect Sizing
 IN PROC. INT. CONF. ON COMPUTER AIDED DESIGN
, 1996
"... In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We define a class of optimization problems as CHposynomial programs and reveal a general dominance property for all CHposynomial programs (Theorem 1). We show that the STIS problems under a number of transi ..."
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Cited by 17 (8 self)
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In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We define a class of optimization problems as CHposynomial programs and reveal a general dominance property for all CHposynomial programs (Theorem 1). We show that the STIS problems under a number of transistor delay models are CHposynomial programs and propose an efficient and nearoptimal STIS algorithm based on the dominance property. When used to solve the simultaneous driver/buffer and wire sizing problem for real designs, it reduces the maximum delay by up to 17.7%, and more significantly, reduces the power consumption by a factor of 61.6%, when compared with the original designs. When used to solve the transistor sizing problem, it achieves a smooth areadelay tradeoff. Moreover, the algorithm optimizes a clock net of 367 drivers/buffers and 59304mlong wire in 120 seconds, and a 32bit adder with 1,026 transistors in 66 seconds on a SPARC5 workstation.
A new approach to simultaneous buffer insertion and wire sizing
 PROC. INT. CONF. ON COMPUTER AIDED DESIGN
, 1997
"... In this paper, we present a completely new approach to the problem of delay minimization by simultaneous buffer insertion and wire sizing for a wire. We show that the problem can be formulated as a convex quadratic program, which is known to be solvable in polynomial time. Nevertheless, we explore s ..."
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Cited by 15 (4 self)
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In this paper, we present a completely new approach to the problem of delay minimization by simultaneous buffer insertion and wire sizing for a wire. We show that the problem can be formulated as a convex quadratic program, which is known to be solvable in polynomial time. Nevertheless, we explore some special properties of our problem and derive an optimal and very efficient algorithm to solve the resulting program. Given m buffers and a set of n discrete choices of wire width, the running time of our algorithm is O(mn²) and is independent of the wire length in practice. For example, an instance of 100 buffers and 100 choices of wire width can be solved in 3 seconds. Besides, our formulation is so versatile that it is easy to consider other objectives like wire area or power dissipation, or to add constraints to the solution. Also, wire capacitance lookup tables, or very general wire capacitance models which can capture area capacitance, fringing capacitance, coupling capacitance, etc. can be used.
Performance Driven Global Routing for Standard Cell Design
, 1997
"... Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect wires, and a greater impact of interconnect on total system performance. These changes have driven a considerable number o ..."
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Cited by 12 (2 self)
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Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect wires, and a greater impact of interconnect on total system performance. These changes have driven a considerable number of studies on singlenet interconnect optimization, but relatively little work has been done to integrate the results on singlenet optimization with the problem of global routing and interconnect optimization for the entire circuit. In this paper, we present the DECIMATE global router for performance driven standard cell design. The router applies both interconnect topology optimization and variablewidth wire sizing optimization results to the global routing problem, while maintaining routing areas that are comparable with TimberWolf Systems' wellknown commercial global router. Optimal selection of interconnection structures is shown to be an NPHard problem; we provide a simple heuristic for the problem, and show that it is effective with experiments on industry benchmarks. Under the Elmore delay model, our global router produces as much as a 35% reduction in critical path delayover TimberWolf Systems' global router, while path length reductions are as large as 52%. Circuit area optimization is performed taking into accountvariablysized wires, fixed routing topologies, and preexisting obstacles; an improved cost function obtains as much as an 11.6% reduction in channel densityover the result in [16].
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing
 IEEE Trans. ComputerAided Design
, 1999
"... Abstract—In this paper, we present a completely new approach to the problem of delay minimization by simultaneous buffer insertion and wire sizing for a wire. We show that the problem can be formulated as a convex quadratic program, which is known to be solvable in polynomial time. Nevertheless, we ..."
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Cited by 12 (2 self)
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Abstract—In this paper, we present a completely new approach to the problem of delay minimization by simultaneous buffer insertion and wire sizing for a wire. We show that the problem can be formulated as a convex quadratic program, which is known to be solvable in polynomial time. Nevertheless, we explore some special properties of our problem and derive an optimal and very efficient algorithm modified active set method (MASM) to solve the resulting program. Given m buffers and a set of n discrete choices of wire width, the running time of our algorithm is O(mn 2) and is independent of the wire length in practice. For example, an instance of 100 buffers and 100 choices of wire width can be solved in 0.92 s. In addition, we extend MASM to consider simultaneous buffer insertion, buffer sizing, and wire sizing. The resulting algorithm MASMBS is again optimal and very efficient. For example, with six choices of buffer size and 10 choices of wire width, the optimal solution for a 15 000 m long wire can be found in 0.05 s. Besides, our formulation is so versatile that it is easy to consider other objectives like wire area or power dissipation, or to add constraints to the solution. Also, wire capacitance lookup tables, or very general wire capacitance models which can capture area capacitance, fringing capacitance, coupling capacitance, etc. can be used. Index Terms—Buffer insertion, buffer sizing, interconnect, optimization, performance optimization, physical design, quadratic programming. I.
Greedy wiresizing is linear time
 in Proc. Int. Symp. Physical Design
, 1998
"... Abstract—The greedy wiresizing algorithm (GWSA) has been experimentally shown to be very efficient, but no mathematical analysis on its convergence rate has ever been reported. In this paper, we consider GWSA for continuous wire sizing. We prove that GWSA converges linearly to the optimal solution, ..."
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Abstract—The greedy wiresizing algorithm (GWSA) has been experimentally shown to be very efficient, but no mathematical analysis on its convergence rate has ever been reported. In this paper, we consider GWSA for continuous wire sizing. We prove that GWSA converges linearly to the optimal solution, which implies that the run time of GWSA is linear with respect to the number of wire segments for any fixed precision of the solution. Moreover, we also prove that this is true for any starting solution. This is a surprising result because previously it was believed that in order to guarantee convergence, GWSA had to start from a solution in which every wire segment is set to the minimum (or maximum) possible width. Our result implies that GWSA can use a good starting solution to achieve faster convergence. We demonstrate this point by showing that the minimization of maximum delay and the minimization of area subject to maximum delay bound using Lagrangian relaxation can be sped up by more than 50%. Index Terms — Interconnect, performance optimization, wiresizing. I.
An efficient approach to multilayer layer assignment with an application to via minimization
 National Taiwan University
, 1999
"... Abstract—In this paper we present an efficient heuristic algorithm for the postlayout layer assignment and via minimization £ problem of multilayer gridless integrated circuit (IC), printed ¤ circuit board (PCB), and multichip module (MCM) layouts. We formulate the multilayer layer assignment probl ..."
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Cited by 12 (0 self)
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Abstract—In this paper we present an efficient heuristic algorithm for the postlayout layer assignment and via minimization £ problem of multilayer gridless integrated circuit (IC), printed ¤ circuit board (PCB), and multichip module (MCM) layouts. We formulate the multilayer layer assignment problem by introducing the notion of the extended conflictcontinuation (ECC) graph. When the formulated ECC graph of a layer assignment problem is a tree, we show that the problem can be solved by an algorithm § which is both linear time and optimal. When the formulated ECC ¨graph is not a tree, we present an algorithm which constructs © a sequence of maximal induced subtrees from the ECC graph, then applies our linear time optimal algorithm to each of the induced subtrees to refine the layer assignment. Our experiments
An efficient and optimal algorithm for simultaneous buffer and wire sizing
 IEEE Trans. ComputerAided Design
, 1999
"... Abstract—In this paper, we consider the problem of interconnect delay minimization by simultaneous buffer and wire sizing under the Elmore delay model. We first present a polynomial time algorithm SBWS to minimize the delay of an interconnect wire. Previously, no polynomial time algorithm for the pr ..."
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Cited by 11 (0 self)
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Abstract—In this paper, we consider the problem of interconnect delay minimization by simultaneous buffer and wire sizing under the Elmore delay model. We first present a polynomial time algorithm SBWS to minimize the delay of an interconnect wire. Previously, no polynomial time algorithm for the problem has been reported in the literature. SBWS is an iterative algorithm with guaranteed convergence to the optimal solution. It runs in quadratic time and uses constant memory for computation. Experimental results show that SBWS is extremely efficient in practice. For example, for an interconnect of 10 000 segments and buffers, the CPU time is only 0.255 s. We then extend our result to handle interconnect trees. We present an algorithm SBWST which always gives the optimal solution. Experimental results show that SBWST is faster than the greedy wire sizing algorithm [2] in practice. Index Terms — Buffer sizing, interconnect, performance optimization, physical design, wire sizing.
Timing optimization for multisource nets: characterization and optimal repeater insertion
 IEEE TRANSATIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
, 1999
"... This paper presents new results in the area of timing optimization for multisource nets. The augmented RCdiameter (ARD) is suggested as a natural and practical performance measure and a linear time algorithm for computing the ARD of a multisource net is presented. Building on the ARD measure, we ch ..."
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Cited by 11 (1 self)
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This paper presents new results in the area of timing optimization for multisource nets. The augmented RCdiameter (ARD) is suggested as a natural and practical performance measure and a linear time algorithm for computing the ARD of a multisource net is presented. Building on the ARD measure, we characterize the multisource optimization problem in terms of operations on piecewise linear functions. This characterization is then used to develop an algorithm for optimal repeater insertion: for a given multisource topology the algorithm efficiently identifies an optimal assignment of repeaters to prescribed insertion points under the “min cost timing feasible” problem formulation. The algorithm has been implemented and computational results demonstrate the viability of the approach.
Wire Width Planning for Interconnect Performance Optimization
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2002
"... In this paper, we study wire width planning for interconnect performance optimization in an interconnectcentric design flow. We first propose some simplified, yet nearoptimal wire sizing schemes, using only one or two discrete wire widths. Our sensitivity study on wire sizing optimization further ..."
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Cited by 10 (1 self)
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In this paper, we study wire width planning for interconnect performance optimization in an interconnectcentric design flow. We first propose some simplified, yet nearoptimal wire sizing schemes, using only one or two discrete wire widths. Our sensitivity study on wire sizing optimization further suggests that there exists a small set of "globally" optimal wire widths for a range of interconnects. We develop general and efficient methods for computing such a "globally" optimal wire width design and show rather surprisingly that using only two "predesigned" widths for each metal layer, we are still able to achieve close to optimal performance compared with that by using many possible widths, not only for one fixed length, but also for all wire lengths assigned at each metal layer. Our wire width planning can consider different design objectives and wire length distributions. Moreover, our method has a predictable small amount of errors compared with optimal solutions. We expect that our simplified wire sizing schemes and wire width planning methodology will be very useful for better design convergence and simpler routing architectures.