We present an extensive, annotated bibliography of the abstract machines designed for each of the main programming paradigms (imperative, object oriented, functional, logic and concurrent). We conclude that whilst a large number of efficient abstract machines have been designed for particular language implementations, relatively little work has been done to design abstract machines in a systematic fashion.

The formal specification of hardware at the instruction level is a daunting task. The complexity, size and intricacies of most instruction sets makes this task even more difficult. However, the benefits of such a specification can be quite rewarding: a precise, unambiguous description is provided for each instruction, a basis for proving the correctness of code transformations is made available, and the specification can be animated, providing a simulator. This paper proposes a high level structural operational semantic (S.O.S.) specification for the class of transport triggered architectures. These architectures are simple, powerful, flexible and modular and can exploit very fine grained parallelism. The S.O.S. is novel in that it follows the structure of the architecture, and by doing so inherits the modularity of the architecture. 1 INTRODUCTION The precise definition of programming languages is important; ambiguities in programming language definitions were rife before the introdu...

A standard technique in compiler construction 2 consists in structuring the compilation of source languages to target code by intermediate levels[21][22][23]. Such an approach is practicable because compilation phases between intermediate levels become simpler and increase the flexibility regarding different source and target codes. Furthermore, recently rediscovered virtual machine technology can be effectively used as an intermediate low-level architecture suitable for supporting serious implementations of a wide variety of programming languages. Additionally, the virtual machines provide several desirable features such as portability, code optimizations, and native machine code generation. Now, we consider this task of constructing intermediatelevel machine architectures and compilers generating code for these architectures in the context of design pattems.