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16
Huffman algebras for independent random variables
 IBM RC
, 1994
"... Based on a rearrangement inequality by Hardy, Littlewood and Polya, we define twooperator algebras for independent random variables. These algebras are called Huffman algebras since the Huffman algorithm on these algebras produces an optimal binary tree that minimizes the weighted lengths of leaves ..."
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Based on a rearrangement inequality by Hardy, Littlewood and Polya, we define twooperator algebras for independent random variables. These algebras are called Huffman algebras since the Huffman algorithm on these algebras produces an optimal binary tree that minimizes the weighted lengths of leaves. Many examples of such algebras are given. For the case with random weights of the leaves, we prove the optimality of the tree constructed by the power of two rule, i.e., the Huffman algorithm assuming identical weights, when the weights of the leaves are independent and identically distributed.
A Fast Algorithm for Area Minimization of Slicing Floorplans
"... The traditional algorithm for area minimization of slicing floorplans due to Stockmeyer has time and space complexity O(n^2) in the worst case. For more than a decade, it has been considered the best possible. This paper presents a new algorithm of worstcase time and space complexity O(n log n), wh ..."
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Cited by 10 (1 self)
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The traditional algorithm for area minimization of slicing floorplans due to Stockmeyer has time and space complexity O(n^2) in the worst case. For more than a decade, it has been considered the best possible. This paper presents a new algorithm of worstcase time and space complexity O(n log n), where n is the total number of realizations for the basic blocks, regardless whether the slicing is balanced or not. We also show Omega(n log n) is the lower bound on the time complexity of any area minimization algorithm. Therefore, the new algorithm not only finds the optimal realization, but also has the optimal running time. Keywords Physical design, floorplanning, area minimization, data structure. I. Introduction A. Problem Description Floorplan design is an important step in the physical design process of VLSI circuits [8]. A floorplan F is a subdivision of an enclosing rectangle by horizontal and vertical line segments into nonoverlapping rectangles. A rectangle not sub...
Dynamic Shannon Coding
, 2005
"... We present a new algorithm for dynamic prefixfree coding, based on Shannon coding. We give a simple analysis and prove a better upper bound on the length of the encoding produced than the corresponding bound for dynamic Huffman coding. We show how our algorithm can be modified for efficient lengthr ..."
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Cited by 9 (7 self)
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We present a new algorithm for dynamic prefixfree coding, based on Shannon coding. We give a simple analysis and prove a better upper bound on the length of the encoding produced than the corresponding bound for dynamic Huffman coding. We show how our algorithm can be modified for efficient lengthrestricted coding, alphabetic coding and coding with unequal letter costs.
Optimal prefix codes for infinite alphabets with nonlinear costs
 IEEE Trans. Inf. Theory
, 2008
"... Abstract — Let P = {p(i)} be a measure of strictly positive probabilities on the set of nonnegative integers. Although the countable number of inputs prevents usage of the Huffman algorithm, there are nontrivial P for which known methods find a source code that is optimal in the sense of minimizing ..."
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Cited by 4 (3 self)
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Abstract — Let P = {p(i)} be a measure of strictly positive probabilities on the set of nonnegative integers. Although the countable number of inputs prevents usage of the Huffman algorithm, there are nontrivial P for which known methods find a source code that is optimal in the sense of minimizing expected codeword length. For some applications, however, a source code should instead minimize one of a family of nonlinear objective P functions, βexponential means, those of the form loga i p(i)an(i) , where n(i) is the length of the ith codeword and a is a positive constant. Applications of such minimizations include a novel problem of maximizing the chance of message receipt in singleshot communications (a < 1) and a previously known problem of minimizing the chance of buffer overflow in a queueing system (a> 1). This paper introduces methods for finding codes optimal for such exponential means. One method applies to geometric distributions, while another applies to distributions with lighter tails. The latter algorithm is applied to Poisson distributions and both are extended to alphabetic codes, as well as to minimizing maximum pointwise redundancy. The aforementioned application of minimizing the chance of buffer overflow is also considered. Index Terms — Communication networks, generalized entropies, generalized means, Golomb codes, Huffman algorithm,
Dynamic LengthRestricted Coding
, 2003
"... Suppose that $S$ is a string of length $m$ drawn from an alphabet of $n$ characters, $d$ of which occur in $S$. Let $P$ be the relative frequency distribution of characters in $S$. We present a new algorithm for dynamic coding that uses at most \(\lceil \lg n \rceil 1\) bits to encode each character ..."
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Cited by 3 (2 self)
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Suppose that $S$ is a string of length $m$ drawn from an alphabet of $n$ characters, $d$ of which occur in $S$. Let $P$ be the relative frequency distribution of characters in $S$. We present a new algorithm for dynamic coding that uses at most \(\lceil \lg n \rceil 1\) bits to encode each character in $S$
Tight bounds on minimum maximum pointwise redundancy
 In Proceedings of the International Symposium on Information Theory
, 1944
"... Abstract — This paper presents new lower and upper bounds for the optimal compression of binary prefix codes in terms of the most probable input symbol, where compression efficiency is determined by the nonlinear codeword length objective of minimizing maximum pointwise redundancy. This objective re ..."
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Cited by 2 (0 self)
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Abstract — This paper presents new lower and upper bounds for the optimal compression of binary prefix codes in terms of the most probable input symbol, where compression efficiency is determined by the nonlinear codeword length objective of minimizing maximum pointwise redundancy. This objective relates to both universal modeling and Shannon coding, and these bounds are tight throughout the interval. The upper bounds also apply to a related objective, that of d th exponential redundancy. I.
Hierarchical Buffered Routing Tree Generation
"... AbstractThis paper presents a solution to the problem of performancedriven buffered routing tree generation for VLSI circuits. Using a novel bottomup construction algorithm and a local neighborhood search strategy, our polynomial time algorithm finds the optimum solution in an exponentialsize s ..."
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AbstractThis paper presents a solution to the problem of performancedriven buffered routing tree generation for VLSI circuits. Using a novel bottomup construction algorithm and a local neighborhood search strategy, our polynomial time algorithm finds the optimum solution in an exponentialsize solution subspace. The final output is a buffered rectilinear Steiner routing tree that connects the driver of a net to its sink nodes. The two variants of the problem, i.e., maximizing the required time at the driver subject to a maximum total area constraint and minimizing the total area subject to a minimum required time at the driver constraint, are handled by propagating threedimensional solution curves during the construction phase. Experimental results demonstrate the effectiveness of our algorithm compared to other techniques. I.
Fanout Optimization under a Submicron TransistorLevel Delay Model
, 1998
"... In this paper we present a new fanout optimization algorithm whichisparticularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class of fanout trees to the socalled bipolar LTtrees, the topology of the optimal fanout tree is found by means of a dynamic pr ..."
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In this paper we present a new fanout optimization algorithm whichisparticularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class of fanout trees to the socalled bipolar LTtrees, the topology of the optimal fanout tree is found by means of a dynamic programming algorithm. The bu#er selection is in turn performed by using a continuous bu#er sizing technique based on a very accurate delay model especially developed for submicron CMOS processes. The fanout trees can distribute a signal with arbitrary polarity from the root of the tree to a set of sinks with arbitrary required time, required minimum signal slope, polarity and capacitive load. These trees can be constructed to maximize the required time at the root or to minimize the total bu#er area under a required time constraint at the root. The performance of the algorithm shows several improvements with respect to conventional fanout optimization methods. More precisely, the area and del...
A New Algorithm for Building Alphabetic Minimax Trees
, 2008
"... We show how to build an alphabetic minimax tree for a sequence W = w1,...,wn of real weights in O(nd log log n) time, where d is the number of distinct integers ⌈wi⌉. We apply this algorithm to building an alphabetic prefix code given a sample. ..."
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We show how to build an alphabetic minimax tree for a sequence W = w1,...,wn of real weights in O(nd log log n) time, where d is the number of distinct integers ⌈wi⌉. We apply this algorithm to building an alphabetic prefix code given a sample.
Characterization and Parameterized Generation of Digital Circuits
"... The development of new architectures for FieldProgrammable Gate Arrays (FPGAs) and other forms of digital circuits, and the computeraided design (CAD) software tools for these devices is greatly hampered by the lack of realistic test circuits or benchmarks that exercise them properly. Benchmarking ..."
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The development of new architectures for FieldProgrammable Gate Arrays (FPGAs) and other forms of digital circuits, and the computeraided design (CAD) software tools for these devices is greatly hampered by the lack of realistic test circuits or benchmarks that exercise them properly. Benchmarking is a crucial process in the design of CAD algorithms, as layout problems are typically NPhard and heuristic algorithms are required. This thesis investigates combinatorial structure in digital circuits. We de ne and analyze a series of graphtheoretic properties of combinational and sequential circuits, including a theoretical characterization of reconvergent fanout and metrics to capture the inherent locality found in handmade or synthesized circuits, and propose a new model for describing sequential and hierarchical circuits. By measuring these characteristics on public and proprietary industrial circuits, we determine a realistic pro le of circuits. From our set of new characteristics, we de ne the new combinatorial problem of parameterized random circuit generation, advancing a new paradigm for benchmarking in computeraided design. We then present a heuristic algorithm which solves it, fully implemented in a publicly available tool, gen. Heuristic methods can only be judged on their