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20
A New Heuristic for Rectilinear Steiner Trees
 In Proc. IEEE Int. Conf. on CAD
"... The minimum rectilinear Steiner tree (RST) problem is one of the fundamental problems in the field of electronic design automation. The problem is NPhard, and much work has been devoted to designing good heuristics and approximation algorithms; to date, the champion in solution quality among RST he ..."
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Cited by 20 (2 self)
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The minimum rectilinear Steiner tree (RST) problem is one of the fundamental problems in the field of electronic design automation. The problem is NPhard, and much work has been devoted to designing good heuristics and approximation algorithms; to date, the champion in solution quality among RST heuristics is the Batched Iterated 1Steiner (BI1S) heuristic of Kahng and Robins. In a recent development, exact RST algorithms have witnessed spectacular progress: The new release of the GeoSteiner code of Warme, Winter, and Zachariasen has average running time comparable to that of the fastest available BI1S implementation, due to Robins. We are thus faced with the paradoxical situation that an exact algorithm for an NPhard problem is competitive in speed with a stateoftheart heuristic for the problem. The main contribution of this paper is a new RST heuristic, which has at its core a recent 3=2 approximation algorithm of Rajagopalan and Vazirani for the metric Steiner tree problem on ...
Spanning Trees in Hypergraphs with Applications to Steiner Trees
, 1998
"... This dissertation examines the geometric Steiner tree problem: given a set of terminals in the plane, find a minimumlength interconnection of those terminals according to some geometric distance metric. In the process, however, it addresses a much more general and widely applicable problem, that of ..."
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Cited by 19 (1 self)
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This dissertation examines the geometric Steiner tree problem: given a set of terminals in the plane, find a minimumlength interconnection of those terminals according to some geometric distance metric. In the process, however, it addresses a much more general and widely applicable problem, that of finding a minimumweight spanning tree in a hypergraph. The geometric Steiner tree problem is known to be NPcomplete for the rectilinear metric, and NPhard for the Euclidean metric. The fastest exact algorithms (in practice) for these problems use two phases: First a small but sufficient set of full Steiner trees (FSTs) is generated and then a Steiner minimal tree is constructed from this set. These phases are called FST generation and FST concatenation, respectively, and an overview of each phase is presented. FST concatenation is almost always the most expensive phase, and has traditionally been accomplished via simple backtrack search or dynamic programming.
TwoDimensional Interleaving Schemes with Repetitions: Constructions and Bounds
 IEEE TRANSACTIONS ON INFORMATION THEORY
, 2002
"... Twodimensional interleaving schemes with repetitions are considered. These schemes are required for the correction of twodimensional bursts (or clusters) of errors in applications such as optical recording and holographic storage. We assume that a cluster of errors may have an arbitrary shape, and ..."
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Cited by 17 (4 self)
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Twodimensional interleaving schemes with repetitions are considered. These schemes are required for the correction of twodimensional bursts (or clusters) of errors in applications such as optical recording and holographic storage. We assume that a cluster of errors may have an arbitrary shape, and is characterized solely by its area l. Thus, an interleaving scheme A(l, r) of strength l with r repetitions is an (infinite) array of integers defined by the property that every integer appears no more than r times in any connected component of area t. The problem is to minimize, for a given l and r, the interleaving degree deg A(l, r ), which is the total number of distinct integers contained in the array. Optimal interleaving schemes for r = 1 (no repetitions) have been devised in earlier work. Here, we consider interleaving schemes for r ≥ 2. Such schemes reduce the overall redundancy, yet are considerably more difficult to construct and analyze. To this end, we generalize the concept of L_1distance and introduce the notions of tristance, quadristance, and more generally rdispersion. We focus on the special class of interleaving schemes, called lattice interleavers, that is akin to the class of linear codes in coding theory. We construct efficient lattice interleavers for r = 2, 3, 4 and some higher values of r. For r = 2, 3 we show that these lattice interleavers are either optimal for all t or asymptotically optimal for t → ∞. We present the results of an extensive computer search that yields the optimal lattice interleavers for r = 2, 3, 4, 5, 6 and l up to about 1000. Finally, we consider an alternative connectivity model for clusters, where two elements in an array are connected if they are adjacent horizontally, vertically, or diagonally. We establish relations between interleavers for this model and interleavers for th...
A Catalog of Hanan Grid Problems
 Networks
, 2000
"... We present a general rectilinear Steiner tree problem in the plane and prove that it is solvable on the Hanan grid of the input points. This result is then used to show that several variants of the ordinary rectilinear Steiner tree problem are solvable on the Hanan grid, including  but not li ..."
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Cited by 10 (2 self)
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We present a general rectilinear Steiner tree problem in the plane and prove that it is solvable on the Hanan grid of the input points. This result is then used to show that several variants of the ordinary rectilinear Steiner tree problem are solvable on the Hanan grid, including  but not limited to  Steiner trees for rectilinear (or isothetic) polygons, obstacleavoiding Steiner trees, group Steiner trees and prizecollecting Steiner trees. Also, the weighted region Steiner tree problem is shown to be solvable on the Hanan grid; this problem has natural applications in VLSI design routing. Finally, we give similar results for other rectilinear problems. 1 Introduction Assume we are given a finite set of points S in the plane. The Hanan grid H(S) of S is obtained by constructing vertical and horizontal lines through each point in S. The main motivation for studying the Hanan grid stems from the fact that it is known to contain a rectilinear Steiner minimum tree (RSMT)...
An O(nlogn) algorithm for obstacleavoiding routing tree construction in the lambdageometry plane
 Proc. ISPD
, 2006
"... Routing is one of the important phases in VLSI/ULSI physical design. The obstacleavoiding rectilinear Steiner minimal tree (OARSMT) construction is an essential part of routing since macro cells, IP blocks, and prerouted nets are often regarded as obstacles in the routing phase. Efficient OARSMT a ..."
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Cited by 6 (0 self)
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Routing is one of the important phases in VLSI/ULSI physical design. The obstacleavoiding rectilinear Steiner minimal tree (OARSMT) construction is an essential part of routing since macro cells, IP blocks, and prerouted nets are often regarded as obstacles in the routing phase. Efficient OARSMT algorithms can be employed in practical routers iteratively. Recently, IC routing and related researches have been extended from Manhattan architecture (λ 2geometry) to Y / Xarchitecture (λ 3 / λ 4geometry) to improve the chip performance. This paper presents an O(nlogn) heuristic, λOASMT, for obstacleavoiding Steiner minimal tree construction in the λgeometry plane. Based on obstacleavoiding constrained Delaunay triangulation, a full connected tree is constructed and then embedded into λOASMT by a novel method called zonal combination. To the best of our knowledge, this is the first work addressing the λOASMT problem. Compared with two most recent works on OARSMT problem, λOASMT obtains up to 30Kx speedup with an even better quality solution. We have tested randomly generated cases with up to 1K terminals and 10K rectilinear obstacles within 3 seconds on a Sun V880 workstation (755MHz CPU and 4GB memory). The high efficiency and accuracy of λOASMT make it extremely practical and useful in the routing phase, as well as interconnect estimation in the process of floorplanning and placement.
BerryEsseen bounds for the number of maxima in planar regions
 ELECTRONIC JOURNAL OF PROBABILITY
, 2003
"... We derive the optimal convergence rate O(n 1/4 ) in the central limit theorem for the number of maxima in random samples chosen uniformly at random from the right triangle of the shape #. A local limit theorem with rate is also derived. The result is then applied to the number of maxima in general ..."
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Cited by 5 (2 self)
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We derive the optimal convergence rate O(n 1/4 ) in the central limit theorem for the number of maxima in random samples chosen uniformly at random from the right triangle of the shape #. A local limit theorem with rate is also derived. The result is then applied to the number of maxima in general planar regions (upperbounded by some smooth decreasing curves) for which a nearoptimal convergence rate to the normal distribution is established.
Efficient MaximaFinding Algorithms for Random Planar Samples
 Discrete Mathematics and Theoretical Computer Science (Electronic
, 2003
"... this paper a simple classification of several known algorithms for finding the maxima, together with several new algorithms; among these are two efficient algorithmsone with expected complexity n +O( # nlogn) when the point samples are issued from some planar regions, and another more efficient t ..."
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Cited by 5 (2 self)
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this paper a simple classification of several known algorithms for finding the maxima, together with several new algorithms; among these are two efficient algorithmsone with expected complexity n +O( # nlogn) when the point samples are issued from some planar regions, and another more efficient than existing ones
An ILP based hierarchical global routing approach for VLSI ASIC design
, 2007
"... The use of integrated circuits in highperformance computing, telecommunications, and consumer electronics has been growing at a very fast pace. The level of integration as measured by the number of logic gates in a chip has been steadily rising due to the rapid progress in processing and intercon ..."
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Cited by 5 (2 self)
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The use of integrated circuits in highperformance computing, telecommunications, and consumer electronics has been growing at a very fast pace. The level of integration as measured by the number of logic gates in a chip has been steadily rising due to the rapid progress in processing and interconnect technology. The interconnect delay in VLSI circuits has become a critical determiner of circuit performance. As a result, circuit layout is starting to play a more important role in today’s chip designs. Global routing is one of the key subproblems of circuit layout which involves finding an approximate path for the wires connecting the elements of the circuit without violating resource constraints. In this paper, several integer programming (ILP) based global routing models are fully investigated and explored. The resulting ILP problem is relaxed and solved as a linear programming (LP) problem followed by a rounding heuristic to obtain an integer solution. Experimental results obtained show that the proposed combined WVEM (wirelength, via, edge capacity) model can optimize several global routing objectives simultaneously and effectively. In addition, several hierarchical methods are combined with the proposed flat ILP based global router to reduce the CPU time by about 66 % on average for edge capacity model (ECM).
Delayrelated Secondary Objectives for Rectilinear Steiner Minimum Trees
 Discrete Applied Mathematics
, 2001
"... The rectilinear Steiner tree problem in the plane is to construct a minimumlength tree interconnecting a set of points (called terminals) consisting of horizontal and vertical line segments only. Rectilinear Steiner minimum trees (RSMTs) can today be computed quickly for realistic instances occ ..."
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Cited by 4 (1 self)
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The rectilinear Steiner tree problem in the plane is to construct a minimumlength tree interconnecting a set of points (called terminals) consisting of horizontal and vertical line segments only. Rectilinear Steiner minimum trees (RSMTs) can today be computed quickly for realistic instances occurring in VLSI design. However, interconnect signal delays are becoming increasingly important in modern chip designs. Therefore, the length of paths or direct delay measures should be taken into account when constructing rectilinear Steiner trees. We consider the problem of nding an RSMT that  as a secondary objective  minimizes a signal delay related objective. Given a source (one of the terminals) we give some structural properties of RSMTs for which the weighted sum of path lengths from the source to the other terminals is minimized. Also, we present exact and heuristic algorithms for constructing RSMTs with weighted sum of path lengths or Elmore delays secondary objectives. Computational results for industrial designs are presented. Research Institute for Discrete Mathematics, University of Bonn, Germany; email: peyer@or.unibonn.de. y Department of Computer Science, University of Copenhagen, Denmark; email: martinz@diku.dk. z Department of Computer Science, University of Copenhagen, Denmark; email: david@diku.dk. 1 1
Rectilinear Group Steiner Trees and Applications in VLSI Design
"... Given a set of disjoint groups of points in the plane, the rectilinear group Steiner tree problem is the problem of finding a shortest interconnection (under the rectilinear metric) which includes at least one point from each group. This is an important generalization of the wellknown rectiline ..."
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Cited by 3 (0 self)
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Given a set of disjoint groups of points in the plane, the rectilinear group Steiner tree problem is the problem of finding a shortest interconnection (under the rectilinear metric) which includes at least one point from each group. This is an important generalization of the wellknown rectilinear Steiner tree problem which has direct applications in VLSI design, i.e., it is the fundamental problem that has to be solved in the detailed routing phase, since the logical units typically allow the nets to connect to several electrically equivalent ports. We present a first (tailored) exact algorithm for solving the rectilinear group Steiner tree problem (and related variants of the problem). The algorithm essentially constructs a subgraph of the corresponding Hanan grid on which existing algorithms for solving the Steiner tree problem in graphs are applied. The reductions of the Hanan grid are performed by applying point deletions and by generating full Steiner trees on the re...