This paper discusses design technology issues for embedded systems using processor cores, with a focus on software compilation tools. Architectural characteristics of contemporary processor cores are reviewed and tool requirements are formulated. This is followed by a comprehensive survey of both existing and new software compilation techniques that are considered important in the context of embedded processors

In this article constructive scheduling methods combined with genetic algorithms are used to searchfor a suitable order to schedule the operations. The method is extended with an encoding capable of allocating supplementary resources during scheduling. This makes it very suitable in high-level synthesis strategies based on lower bound estimations techniques. Experiments and comparisons show high quality results and fast run times that outperform results produced by other heuristic scheduling methods 1 Introduction During high-level synthesis a behavioral description of a chip is translated into a digital network structure [McFa90]. The behavioral description consists of calculations (like additions, multiplications, logical operations etc.) and control structures (like conditionals, loops and procedure calls) which are used to transform input data into output data. The digital network structure consists of functional modules (adders, multipliers, ALUs, logical gates), storage (like r...

As methodologies and tools for chip-level design mature, design effort becomes focused on increasingly higher levels of abstraction. Presently much effort is focused on the system level of design, where the key design tasks include system component allocation, functional partitioning and transformation, and coarse estimation. However, the commonly used internal formats of functionality, such as the control-dataflow graph, are too fine-grained for the system level. We introduce a new, more abstract internal format, and we describe how it enables estimations of design metrics in an order of magnitude less time and memory, as well as enabling truly practical designer interaction. The format serves as the core of the SpecSyn system design environment, and it can be extended to handle a large scope of new and evolving system design problems. . Contents 1 Introduction 1 2 SLIF definition 2 2.1 Requirements of an internal format : : : : : : : : : : : : : : : : : : : : : : : 2 2.2 Basic ...

In this paper a unified approach of lower bound functional area and cycle budget estimations is presented to predict area--delay characteristics of designs at system level. The estimations are mainly based on relaxing precedence constraints in a behavioral design description and are the most accurate estimations reported to date. 1. Introduction In high--level synthesis, a data path consisting of modules (i.e. functional units), registers and interconnection units is synthesized from a behavioral design description [McFa90]. Such a description is represented by a data flow graph (DFG), which is a translation of an algorithmic specification in a hardware description language [Eijnd92]. The ability to predict the area--delay characteristics of designs without actually implementing them is important in producing quality designs in a reasonable time, and is therefore an important part of an (interactive) system design environment [Fleu93]. If a design will be part of a larger system, then...

Introduction Mobile and personal communication systems, and multi-media are among the most prominently growing sectors of the electronics industry today. As an illustration, Figure 1 gives an indication of the volume of some personal communication applications in the European market. New business and home applications are emerging, using advanced communication media such as satellite links, cellular radio, or high-speed optical networks. The success of these developments will however depend to a great extent on the ability to realise complex digital signal processing functionalities in cost-efficient VLSI chips. 1990 1992 1994 1996 40 30 20 10 0 Million users Cordless Cellular Paging Private mobile Figure 1. European market of personal communication systems (source : Elsevier Advanced Technology). The design of these chips is subject to stringent requirements in terms of processing performance and power dissipation. At the same

System specification and design consists of describing a system's desired functionality, and of mapping that functionality for implementation on a set of system components, such as processors, ASIC's, memories, and buses. In this article, we describe the key problems of system specification and design, including specification capture, design exploration, hierarchical modeling, software and hardware synthesis, and cosimulation. We highlight existing tools and methods for solving those problems, and we discuss issues that remain to be solved. 1 Introduction Embedded systems have become commonplace in recent years. Examples include automobile cruise-control, fuel-injection systems, aircraft autopilots, telecommunication products, interactive television processors, network switches, video focusing units, robot controllers, and numerous medical devices. While there is no widespread agreement of what defines an embedded system, we note that such systems possess a few key characteristics. Th...

In this paper a flexible interface to high-level synthesis data (NEAT) is presented. NEAT offers three design views to common high-level synthesis data domains. Inter- and intra-domain relations are used to represent design relations between synthesis objects and to store synthesis results. To extend the functionality of the common synthesis interface programmers use object oriented programming techniques to create their own specific synthesis interface. Interaction between high-level synthesis tools is achieved by exchanging data using a common file-format, which can easily be extended. A graphical interface hasbeen established to allow interactive interpretation and manipulation of synthesis results. NEAT offers unlimited extendibility and no restrictions towards synthesis trajectories, and therefore is highly suitable as a research platform. 1 Introduction High-level synthesis converts behavioral descriptions of chips into digital network structures consisting of register-transfer...

Recently a number of heuristic based system-level synthesis algorithms have been proposed. Though these algorithms quickly generate good solutions, how close these solutions are to optimal is a question that is difficult to answer. While current exact techniques produce optimal results, they fail to produce them in reasonable time. This paper presents a synthesis algorithm that produces solutions of guaranteed quality (optimal in most cases or within a known bound) with practical synthesis times (few seconds to minutes). It takes a unified look (the lack of which is one of the main sources of sub-optimality in the heuristic techniques) at different aspects of system synthesis such as pipelining, selection, allocation, scheduling and FPGA reconfiguration. Our technique can handle both time constrained as well as resource constrained synthesis problems. We present results of our algorithm implemented as part of the Match project [1] at Northwestern University. 1.