The application of adaptive power-supply regulation is extended to serial links. The adaptive supply maximizes the energy -efficiency of the I/O circuits and serves as a global bias to scale the link properties optimally with the bitrate. Parallelism in transceivers and the use of multiphase clocks increase the bitrate to a multiple of the clock frequency and, hence, enable the lowfrequency low-voltage operation to reduce power while meeting the specified bitrate. Two key designs to enable this power saving are presented: parallelized transceivers for low-voltage operation and dual-loop architecture phase/delay-locked loop for multiphase clock distribution. A prototype chip fabricated in 0.25- m CMOS process operates at 0.65--5.0 Gb/s while dissipating 9.7--380 mW.

Abstract—The constraints on the design of CMOS operational amplifiers with rail-to-rail input range for extremely low supply voltage operation, are addressed. Two design approaches for amplifiers based on complementary input differential pairs and a single input pair, respectively, are presented. The first realizes a feedforward action to accommodate the common-mode (CM) component of the input signals to the amplifier input range. The second approach performs a negative feedback action over the input CM signal. Two operational amplifiers based on the proposed approaches have been designed for 1-V total supply operation, and fabricated in a standard 1.2-μm CMOS process. Experimental results are provided and the corresponding performances are discussed and compared. Index Terms—CMOS analog integrated circuits, low voltage, operational amplifiers, rail-to-rail operation. I.

Abstract—This work presents a study of the extended counting technique for a 1.2-V micropower voice-band A/D converter. This extended counting technique is a blend of 61 modulation with its high resolution but relatively low speed and algorithmic conversion with its higher speed but lower accuracy. To achieve this, the converter successively operates first as a first-order 61 modulator to convert the most significant bits, and then the same hardware is used as an algorithmic converter to convert the remaining least significant bits. An experimental prototype was designed in 0.8- m CMOS. With a 1.2-V power supply, it consumes 150 W of power at a 16-kHz Nyquist sampling frequency. The measured peak ƒ @x C „rhA was 80 dB and the dynamic range 82 dB. The converter core including the controller and all reconstruction logic occupies about I Q I mmP of chip area. This is considerably less than a complete 61 modulation A/D converter where the digital decimation filter would occupy a significant amount of chip area. Index Terms—Analog-to-digital, extended counting, low power, low voltage. I.

A fully differential opamp suitable for very-low voltage switched-capacitor circuits in standard CMOS technologies is introduced. The proposed two stage opamp needs a simple low voltage CMFB switched-capacitor circuit only for the second stage. Due to the reduced supply voltage, the CMFB circuit is implemented using bootstrapped switches. Minor modifications allow to use chopper stabilization for flicker noise reduction. Two different compensation schemes are discussed and compared using an example for 1V operation of the amplifier.

Portable electronic systems require low-voltage low-power building blocks. An important building block is an A/D converter. ΔΣ ADCs provide an efficient way of trading off speed for resolution. The switched opamp (SO) technique allows design of switched-capacitor (SC) circuits at very low supply voltage without the use of multithreshold technologies or voltage multipliers to drive the switches [1]. The basic idea of it is to leave out the switches connected to the output of the amplifier in a SC integrator, because those are the ones that fail to conduct when the supply voltage is low. Switches can only be connected to well-chosen reference voltages. In this implementation the differential modified SO integrator cell is used, so the reference voltages are V SS and V DD [2]. This allows maximum overdrive of V DD-V SS for the switches. For low-voltage low-power applications, a single loop ΔΣ topology is preferable over a cascade because of its reduced sensitivity to linear integrator non-idealities, such as OTA gain, GBW and switch resistance. Low supply voltage makes it impossible to use cascode transistors in the output stage to increase gain, while for the same GBW, a two-stage amplifier will consume a multiple of the power of a single-stage one. A single-loop architecture operates with the gain provided by a one stage amplifier and therefore facilitates low-power operation. To design for lowpower, it is important to realize the following: 1) The SNR must be limited by thermal noise (kT/C) and not by quantization noise [3]. 2) The first integrator needs a large sampling capacitor to reduce the kT/C noise to the required level. 3) Noise sources inside the loop are suppressed, so the other integrators can be scaled down. In this design the sampling capacitor of the 2 nd and 3 rd OTA are 10 times smaller than the input sampling capacitor. Consequently, the first integrator consumes the major part of the power. A large power saving is obtained on the architectural level. The basic SO integrator transfer function is

The continued drive toward technology scaling in VLSI design has provided greater integration levels in silicon chips. Thanks to the reduction in minimum feature size and the corresponding decrease in power supply voltage, digital circuits have bene-fited from savings in area and power consumption. This approach presents a number of challenges in Complementary Metal-Oxide Semiconductor (CMOS) analog circuit design. As the gate oxide of transistors becomes thinner and power consumption increases, a lower supply voltage must be used, even though it results in performance degradation of analog circuits. This must be done in order to avoid silicon punch-through. In applications requiring low power consumption and moderate conversion speed, one of the most frequently used analog-to-digital converter (ADC) architec-tures is the successive approximation. As data converters are mixed-signal circuits, containing both analog and digital circuits, they suffer from the same problems just described. This thesis presents the design of a low-voltage successive approximation ADC based on a Switched Opamp comparator. The proposed comparator archi-

A circuit for generating reference voltages for an A/D converter is presented. The circuit consisting of a bandgap reference and a driver circuit is capable of operating on sub 1-volt supply voltages. The circuit is designed using a standard 0.5 #m CMOS technology. Simulations show maximum 0.24% variation in the generated reference voltage over a temperature range from-20 Cto 100 C and a supply voltage range from 0.95 V to 1.50 V. The circuit is capable of driving a 2 pF switched capacitor load at 5 MHz clock rate while consuming 450 #W of power from a 1.0 V supply.

In this paper, a very low-voltage fourth-order bandpass delta-sigma modulator with a two-path architecture is presented. Using the modified switched opamp technique enables the modulator to operate at only 0.8 V supply voltage without any voltage multiplier or bootstrapping switch. Realized in a 0.25-m 1P5M standard CMOS process, the prototype modulator exhibits a signal-to-noise-plusdistortion ratio (SNDR) of 60.6 db and a dynamic range (DR) of 68 db in a 30 KHz signal bandwidth centered at 1.25 MHz while consuming 2.5 mW and occupying an active area of 2.11 mm .

A simple series switch sizing procedure is presented taking into account very low-voltage switch operation. Under these conditions, the switch conducts not only in the linear region, but also in saturation. The procedure has been implemented in an automatic sizing tool and used to optimize separately switch sizes in a very low-voltage Delta-Sigma modulator. This has allowed to minimize clock feedthrough while satisfying all settling requirements.

audio ADC is presented. A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. A three-level quantizer with simple dynamic element matching was used to improve linearity. The prototype IC implemented in a 0.13 m CMOS process achieves 92 dB DR, 91 dB SNR and 89 dB SNDR in a 24 kHz audio signal bandwidth, while consuming 1.5 mW from a 0.9 V supply. The prototype operates from 0.65 V to 1.5 V supply with minimal performance degradation. Index Terms—Audio ADC, delta-sigma ADC, double sampling, low voltage, switched-RC. Fig. 1. Double-sampling switched-capacitor integrator circuit. I.