The study of computing is split at an early stage between the separate branches that deal with hardware and software; there is also a corresponding split in later professional specialisation. This paper explores the essential unity of the two branches and attempts to point to a common framework within which hardware-software codesigns can be expressed as a single executable specification, reasoned about, and transformed into implementations. We also describe a hardware/software co-design environment which has been built, and we show how designs can be realised within this environment. A rapid development cycle is achieved by using FPGAs to host the hardware components of the system. The architecture of a hardware platform for supporting experimental hardware/software co-designs is presented. A particular example of a real-time video processing application built using this design environment is also described. 1 Introduction. Our approach to unifying the traditionally separate discipli...

This paper describes a framework and tools for automating the production of designs which can be partially reconfigured at run time. The tools include: (i) a partial evaluator, which produces configuration files for a given design, where the number of configurations can be minimised by a process known as compile-time sequencing; (ii) an incremental configuration calculator, which takes the output of the partial evaluator and generates an initial configuration file and incremental configuration files that partially update preceding configurations; (iii) a tool which further optimises designs for FPGAs supporting simultaneous configuration of multiple cells. While many of our techniques are independent of the design language and device used, our tools currently target Xilinx 6200 devices. Simultaneous configuration, for example, can be used to reduce the time for reconfiguring an adder to a subtractor from time linear with respect to its size to constant time at best and logarithmic time at worst.

FPGA-based synthesis tools require information about behaviour and architectural to make effective use of the limited number of cells typically available. A hardware description language which models layout and behaviour is used to elegantly specify circuit architecture. This source level information is used to efficiently translate circuit descriptions onto FPGA devices. 1 Introduction FPGAs offer many advantages for many kinds of applications and present new opportunities for system design [DeHon 94], but their main disadvantages are the limited number of cells available on a single chip and the difficulty of performing global communication. It is important that the available cells are utilized efficiently . One way to do this is to design circuits with a low level schematic editor and manually configure the cells and routing elements. Although this method allows the realization of highly optimised hardware, it has several shortcomings. Design at the gate level is error prone, and c...

We present an experimental framework for mapping declarative programs, written in a language known as Ruby, into various combinations of hardware and software. Strategies for parametrised partitioning into hardware and software can be captured concisely in this framework, and their validity can be checked using algebraic reasoning. The method has been used to guide the development of prototype compilers capable of producing, from a Ruby expression, a variety of implementations involving fieldprogrammable gate arrays (FPGAs) and microprocessors. The viability of this approach is illustrated using a number of examples for two reconfigurable systems, one containing an array of Algotronix devices and a PC host, and the other containing a transputer and a Xilinx device. 1 Introduction Although it has been known for many years that, from a functional point of view, there is little distinction between hardware and software, in current practice they are mostly developed using very different m...

This paper describes a framework and tools for automating the production of designs that can be partially reconfigured at run time. The approach involves several stages, including: (i) a partial evaluation stage, which produces configuration files for a given design, where the number of configurations are minimised during the compile-time sequencing stage# (ii) an incremental configuration calculation stage, which takes the output of the partial evaluator and generates an initial configuration file and incremental configuration files that partially update preceding configurations# (iii) an optimisation stage for devices or systems supporting simultaneous configuration of multiple components. While many of our techniques are independent of the design language and device used, experimental tools have been developed that target Xilinx 6200 devices. Simultaneous configuration, for example, can be used to reduce the time for reconfiguring an adder to a subtractor from time linear with respe...

As VLSI technology continues to improve, configurable hardware devices such as PLDs are progressively replacing many specialized digital integrated circuits. Field-programmable gate arrays (FPGAs) are one class of such devices, characterized by their ability to be reconfigured as often as desired. Lately, FPGAs have advanced to the stage where they can host large computational circuits, giving rise to the study of reconfigurable computing as a potential alternative to traditional microprocessors. Most previous reconfigurable computers, however, have been ad hoc designs that are not fully compatible with existing general-purpose computing paradigms. This thesis

. Binomial filters are simple and efficient structures based on the binomial coefficients for implementing Gaussian filtering. They do not require multipliers and can therefore be implemented efficiently in programmable hardware. There are many possible variations of the basic binomial filter structure, and they provide a wide range of space-time trade-offs; a number of these designs have been captured in a parametrised form and their features are compared. This technique can be used for multi-dimensional filtering, provided that the filter is separable. The numerical performance of binomial filters, and their implementation using field-programmable devices for an image processing application, are also discussed. Keywords: Gaussian filters, binomial filters, parametrised design, field-programmable devices. 1. Introduction Gaussian filtering is probably the most common form of linear filtering. To overcome the problem of choosing filter coefficients against a set of conflicting constr...

Custom computingmachines, a class of computational platforms consisting of recon#gurable functional units with recon#gurable interconnection networks, provide a middle-groundbetween specialpurpose hardware, which provide high execution speed, and general-purpose computers, which o#er #exibility. The Splash-2 system, onesuch custom computingmachine, is an experimental platform for complex computations requiringthe high speed of special-purpose hardware. The recon#gurabilityandmodularity of Splash-2, along withautomated synthesis tools, allow for rapid, staged developmentofapplications. This paper demonstrates theapplicability of Splash-2 totheimage-processing area and gives an introduction to the programmingenvironment used in developingapplications. An example image-processingapplication based upon two-dimensional convolution is described andtheoperating procedures of custom computingmachines are presented. Also presented are thedetails of directly implementingtwo-dimensional convolution in a straight-forward, systolic fashion in recon#gurable hardware. Keywords: custom computingmachines, convolution, image processing, high performance computing, real time processing 1.

The use of on-board vision with small autonomous robots has been made possible by the advances in the field of Field Programmable Gate Array (FPGA) technology. By connecting a CMOS camera to an FPGA board, on-board vision has been used to reduce the computation time inherent in vision algorithms. The FPGA board allows the user to create custom hardware in a faster, safer, and more easily verifiable manner that decreases the computation time and allows the vision to be done in real-time. Real-time vision tasks for small autonomous robots include object tracking, obstacle detection and avoidance, and path planning. Competitions were created to demonstrate that our algorithms work with our small autonomous vehicles in dealing with these problems. These competitions include Mouse-Trapped-in-a-Box, where the robot has to detect the edges of a box that it is trapped in and move towards them without touching them; Obstacle Avoidance, where an obstacle is placed at any arbitrary point in front of the robot and the robot has to navigate itself around the obstacle; Canyon Following, where the robot has to move to the center of a canyon and follow the canyon walls trying to stay in the center; the Grand Challenge, where the robot had to navigate a hallway and return to its original position in a given amount of time; and Stereo Vision, where a separate robot had to catch tennis balls launched from an air powered cannon. Teams competed on each of these competitions that were designed for a graduate-level robotic vision class, and each team had to develop their own algorithm and hardware components. This paper discusses one team’s approach to each of these problems.

this document which have been, and continue to be, a genuinely inter-disciplinary collaborative venture. In addition, Tony Hoare and Bob McLatchie have been strongly supportive of this work in every way, Bernard Sufrin has provided us with much help on the use of Standard ML, Richard Bird has contributed new algorithms for shared expression extraction, Mark Josephs and Jelio Yantchev have provided useful input on asynchronous models and routing networks. References