This paper describes a framework and tools for automating the production of designs which can be partially reconfigured at run time. The tools include: (i) a partial evaluator, which produces configuration files for a given design, where the number of configurations can be minimised by a process known as compile-time sequencing; (ii) an incremental configuration calculator, which takes the output of the partial evaluator and generates an initial configuration file and incremental configuration files that partially update preceding configurations; (iii) a tool which further optimises designs for FPGAs supporting simultaneous configuration of multiple cells. While many of our techniques are independent of the design language and device used, our tools currently target Xilinx 6200 devices. Simultaneous configuration, for example, can be used to reduce the time for reconfiguring an adder to a subtractor from time linear with respect to its size to constant time at best and logarithmic time at worst.

Abstract. Pebble is a simple language designed to improve the productivity and effectiveness of hardware design. It improves productivity by adopting reusable word-level and bit-level descriptions which can be customised by different parameter values, such as design size and the number of pipeline stages. Such descriptions can be compiled without flattening into various VHDL dialects. Pebble improves design effectiveness by supporting optional constraint descriptions, such as placement attributes, at various levels of abstraction; it also supports run-time reconfigurable design. We introduce Pebble and the associated tools, and illustrate their application to VHDL library development and reconfigurable designs for Field Programmable Gate Arrays (FPGAs). 1

This paper describes a method that automates a key step in producing run-time reconfigurable designs: the identification and mapping of reconfigurable regions. In this method, two successive circuit configurations are matched to locate the components common to them, so that reconfiguration time can be minimized. The circuit configurations are represented as a weighted bipartite graph, to which an efficient matching algorithm is applied. Our method, which supports hierarchical and library-based design, is deviceindependent and has been tested using Xilinx 6200 FPGAs. A number of examples in arithmetic, pattern matching and image processing are selected to illustrate our approach. 1 Introduction Hardware designers are used to develop circuits over space. Reconfigurable devices, such as SRAM-based FPGAs, provide an additional dimension: circuits can be spread over time as well. This flexibility enables a new design style of `hardware-on-demand' or `just-in-time processing ' where circuit...

Pipeline morphing is a simple but effectivetechnique for reconfiguring pipelined FPGA designs at run time. By overlapping computation and reconfiguration, the latency associated with emptying and refilling a pipeline can be avoided. Weshowhow morphing can be applied to linear and mesh pipelines at both word-level and bit-level, and explain how this method can be implemented using Xilinx 6200 FPGAs. We also present an approach using morphing to map a large virtual pipeline onto a small physical pipeline, and the trade-offs involved are discussed.

This paper describes a framework and tools for automating the production of designs that can be partially reconfigured at run time. The approach involves several stages, including: (i) a partial evaluation stage, which produces configuration files for a given design, where the number of configurations are minimised during the compile-time sequencing stage# (ii) an incremental configuration calculation stage, which takes the output of the partial evaluator and generates an initial configuration file and incremental configuration files that partially update preceding configurations# (iii) an optimisation stage for devices or systems supporting simultaneous configuration of multiple components. While many of our techniques are independent of the design language and device used, experimental tools have been developed that target Xilinx 6200 devices. Simultaneous configuration, for example, can be used to reduce the time for reconfiguring an adder to a subtractor from time linear with respe...

A method for managing reconfigurable designs, which supports run-time configuration transformation, is proposed. This method involves structuring the reconfiguration manager into three components: a monitor, a loader, and a configuration store. Different trade-offs can be achieved in configuration time, optimality of the configured circuits, and the complexity of the reconfiguration manager, depending on the reconfiguration methods and the amount of run-time information available at compile time. The proposed techniques, implementable in hardware or software, are supported by our tools and can be applied to both partially and non-partially reconfigurable devices. We describe the combined and the partitioned reconfiguration methods, and use them to illustrate the techniques and the associated trade-offs.

Recon gurable computing involves adapting hardware resources to the speci c needs of applications in order to obtain performance bene ts. This emerging architectural paradigm holds some promise for delivering signi cant speedups to compute{bound applications. However, many challenges need to be overcome before recon gurable computing becomes mainstream. Signi cantly, supporting applications design and providing a convenient run{time environment create opportunities to propose and in-vestigate new ways of managing chip resources. In examining the potential bene ts of providing operating systems support for recon gurable processors, this paper identi-es opportunities for the development of policies for dynamic hardware management and strategies for communicating design ideas to the run{time management system. 1

Reconfigurable computing is a new paradigm based on dynamically adapting the hardware to reconfigure the computation and communication structures on the chip. Re-configurable circuits and systems have evolved fromapplication specific accelerators to a general purpose computing paradigm. Various reconfigurable devices have been de-veloped by researchers and the industry. These devices promise a high degree of flexi-bility and superior performance. But, the algorithmic techniques and software tools are also heavily based on the hardware paradigm from which they have evolved. This thesis addresses the fundamental challenges in achieving high performance us-ing reconfigurable architectures. The diverse range of issues in mapping applications onto reconfigurable architectures are identified. A formal framework for mapping ap-plication tasks onto reconfigurable architectures is proposed in this thesis. The pro-posed framework includes a parameterized system level model, algorithmic mapping techniques and system level interpretive simulation environment. A parameterized model of hybrid reconfigurable architectures, Hybrid System Ar-chitecture Model (HySAM), is developed to facilitate application mapping. Hybrid re-configurable architectures include traditional processing units and memory on the same die as reconfigurable logic. The parameterized abstract model, HySAM, is general enough to capture a wide range of configurable systems. Loop statements in traditional pro-grams consist of regular, repetitive computations which are the most likely candidates for performance enhancement using configurable hardware. This thesis develops a for-mal methodology for mapping loops onto reconfigurable architectures. The abstract model is used to define and solve the problem of mapping loop statements onto reconfig-urable architectures. The complexity of the problems and our proposed solutions is also addressed. Performance improvements are achieved on various architectures using our algorithmic techniques for mapping. In addition, existing design and simulation tools do not include the reconfiguration aspect in their methodology. A simulation methodology for reconfigurable architectures is proposed and validated by implementing a proof of concept tool. The Dynamically Reconfigurable systems Interpretive simulation and Vi-sualization Environment (DRIVE) facilitates high level performance evaluation frame-work for design space exploration.

. We describe the hardware and software extensions that transform a PC-based low-cost FPGA system into a reconfigurable engine for real-time video processing. The hardware extensions include a daughter board for the FPGA system which handles analog and digital colour video conversion. The software extensions include reusable libraries, development tools and a run-time environment. Applications include linear and non-linear filtering, edge detection, image rotation, histogram equalisation, colour identification, motion tracking, and creation of video effects. Our system has been used for research involving video processing, run-time reconfigurable circuits, and hardware/software co-design. 1 Introduction Real-time video is becoming increasingly popular with the proliferation of lowcost video cameras, camcorders and other facilities. Real-time video processing, however, is among the most demanding computation tasks [1]. Applicationspecific integrated circuits can deliver implementations...

Current simulation tools for reconfigurable systems are based on low level simulation of application designs developed in a High-level Description Language(HDL) on HDL models of architectures. This necessitates expertise on behalf of the user to generate the low level design before performance analysis can be accomplished. Most of the current simulation tools also are based on static designs and do not support analysis of dynamic reconfiguration. We propose a novel interpretive simulation and visualization environment which alleviates these problems. The Dynamically Reconfigurable systems Interpretive simulation and Visualization Environment (DRIVE) framework can be utilized for performance evaluation and architecture and design space exploration. Interpretive simulation measures the performance of an application by executing an abstract application model on an abstract parameterized system architecture model. The simulation and visualization framework is being developed in Java language and supports modularity and extensibility. A prototype version of the DRIVE framework has been implemented and the complete framework will be available to the community.