. The satisfiability (SAT) problem is a core problem in mathematical logic and computing theory. In practice, SAT is fundamental in solving many problems in automated reasoning, computer-aided design, computeraided manufacturing, machine vision, database, robotics, integrated circuit design, computer architecture design, and computer network design. Traditional methods treat SAT as a discrete, constrained decision problem. In recent years, many optimization methods, parallel algorithms, and practical techniques have been developed for solving SAT. In this survey, we present a general framework (an algorithm space) that integrates existing SAT algorithms into a unified perspective. We describe sequential and parallel SAT algorithms including variable splitting, resolution, local search, global optimization, mathematical programming, and practical SAT algorithms. We give performance evaluation of some existing SAT algorithms. Finally, we provide a set of practical applications of the sat...

Ahtract-Diagrams are widely used in several areas of computer wience, and their effectiveness is thoroughly recognized. One of the main qualities requested for them is readability; this is especially, but not exclusively, true in the area of information systems, where diagrams are used to model data and functions of the application. Up to now, diagrams have been produced manually or with the aid of a graphic editor; in both caws placement of symbols and routing of connections are under responsi-bility of the designer. The goal of the work is to investigate how readability of diagrams can be achieved by means of automatic tools. Existing results in the literature are compared, and a comprehensive algorithmic approach to the problem is proposed. The algorithm presented draws graphs on a grid and is suitable for both undirected graphs and mixed graphs that contain as subgraphs hierarchic structures. Finally, several applications of a graphic tool that embodies the aforementioned facility are shown. I.

VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasis on standard ce11and macro

This paper addresses several issues involved for routing in Field-Programmable Gate Arrays (FPGAs) that have both horizontal and vertical routing channels, with wire segments of various lengths. Routing is studied by using CAD routing tools to map a set of benchmark circuits into FPGAs, and measuring the effects that various parameters of the CAD tools have on the implementation of the circuits. A two-stage routing strategy of global followed by detailed routing is used, and the effects of both of these CAD stages are discussed, with emphasis on detailed routing. We present a new detailed routing algorithm designed specifically for the types of routing structures found in the most recent generation of FPGAs, and show that the new algorithm achieves significantly better results than previously published FPGA routers with respect to the speed-performance of implemented circuits. The experiments presented in this paper address both of the key metrics for FPGA routing tools, namely the eff...

This paper describes a new detailed routing algorithm that has been designed specifically for the types of routing architectures that are found in the most recent generation of Field-Programmable Gate Arrays (FPGAs). The router is intended for FPGAs that fit within the symmetrical category, which means that the architecture consists of rows and columns of logic cells with both vertical and horizontal routing channels. The routing algorithm, called SEGA, is unique in that it focuses on not only the issue of achieving successful routing of 100 percent of the required connections for a circuit, but also addresses the allocation of wire segments to connections in a way that matches the lengths of the segments to the lengths of the connections. The implementation of the SEGA program is designed in a way that supports a wide range of routing architectures, making the algorithm useful as a research vehicle for exploring new architectures for future FPGAs. SEGA has been used to obtain excelle...

This paper presents a system level approach for the synthesis of hard real-time multitask application specific systems. The algorithm takes into account task precedence constraints among multiple hard real-time tasks and targets a multiprocessor system consisting of a set of heterogeneous off-the-shelf processors. The optimization goal is to select a minimal cost multi-subset of processors while satisfying all the required timing and precedence constraints. There are three design phases: resource allocation, assignment, and scheduling. Since the resource allocation is a search for a minimal cost multi-subset of processors, we adopted an A* search based technique for the first synthesis phase. A variation of the force-directed optimization technique is used to assign a task to an allocated processor. The final scheduling of a hard-real time task is done by the task level scheduler which is based on Earliest Deadline First (EDF) scheduling policy. Our task level scheduler incorporates force-directed scheduling methodology to address the situations where EDF is not optimal. The experimental results on a variety of examples show that the approach is highly effective and efficient.

This dissertation examines a number of geometric interconnection, partitioning, and placement problems arising in the field of VLSI physical design automation. In particular, many of the results concern the geometric Steiner tree problem: given a set of terminals in the plane, find a minimum-length interconnection of those terminals according to some geometric distance metric. Two new algorithms are introduced that compute optimal rectilinear Steiner trees. Both are provably faster than any previous algorithm for instances small enough to solve in practice, and both are also fast in practice. The first algorithm is a dynamic programming algorithm based on decomposing a rectilinear Steiner tree into full trees. A full tree is a Steiner tree in which every terminal is a leaf. Its time complexity is O(n3^n), where n is the number of terminals. The second algorithm modifies the first by the use of full-set screening, which is a process by which some candidate full trees are eliminated f...

A theory of designing is proposed, developed, and illustrated with examples from the domain of physical form. Designing is seen as the exploration of alternative sets of constraints and of the regions of alternative solutions they bound. Designers with different objectives reach different solutions within the same set of constraints, as do designers with the same objectives operating under different constraints. Constraints represent design rules, relations, conventions, and natural laws to be maintained. Some constraints and objectives are given at the outset of a design but many more are adopted along the way. Varying the constraints and the objectives is part of the design process. The theory accounts for various kinds of expertise in designing: knowledge of particular constraints in a design domain; inference--calculating the consequences of design decisions; preference--using objectives to guide decision-making; and partitioning--skill in dividing a large and complicated design into sets of simpler pieces, and understanding the dependencies between decisions. The ability to manage ambiguity and vagueness is an important aspect of design expertise. A computational model supporting the theory is proposed and its implementation discussed briefly. The constraint explorer, a computational environment for designing based on constraint descriptions is described. We see how the constraint explorer might be used in connection with a simple space-planning problem. The problem is taken from the procedures of the Stichting Architecten Research (S.A.R.), a specific architectural design methodology developed to help architects systematically explore layout variability in alternative floorplan designs. Finally, a selected review of related work in constraint-based programming environments, architectural design methods, and the intersection of the two fields is presented.

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This report describes the problem of printed circuit board routing. An overview of circuit board construction is given. The algorithms in a printed circuit board router used for fully automatic routing of highdensity circuit boards are described. Running times of a few minutes have resulted from a new data structure for efficient representation of the routing grid, quick searches for optimal solutions, and generalizations of Lee's algorithm for maze routing. 1 1. Introduction Even though printed circuit board routing is a venerable problem in computer-aided design, fully automatic routing of densely packed boards remains an elusive goal. In current industry practice, a program is used to make most connections automatically. The remainder is left for manual completion. This procedure is a poor second to fully automatic routing. It leaves the possibility for introducing errors in the routing of the final connections. More seriously, it is an investment in time and effort that makes s...