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52
PBS: A backtrack search pseudo Boolean solver
 In Symposium on the theory and applications of satisfiability testing (SAT
, 2002
"... in areas such as hardware and software verification, FPGA routing, planning in AI, etc. Further uses are complicated by the need to express “counting constraints ” in conjunctive normal form (CNF). Expressing such constraints by pure CNF leads to more complex SAT instances. Alternatively, those cons ..."
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Cited by 82 (1 self)
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in areas such as hardware and software verification, FPGA routing, planning in AI, etc. Further uses are complicated by the need to express “counting constraints ” in conjunctive normal form (CNF). Expressing such constraints by pure CNF leads to more complex SAT instances. Alternatively, those constraints can be handled by Integer Linear Programming (ILP), but offtheshelf ILP solvers tend to ignore the Boolean nature of 01 variables. This work attempts to generalize recent highly successful SAT techniques to new applications. First, we extend the basic DavisPutnam framework to handle counting constraints and apply it to solve routing problems. Our implementation outperforms previously reported solvers for the satisfiability with “pseudoBoolean ” constraints and shows significant speedup over best SAT solvers when such constraints are translated into CNF,. Additionally, we solve instances of the MaxONEs optimization problem which seeks to maximize the number of “true ” values over all satisfying assignments. This, and the related MinONEs problem are important due to reductions from MaxClique and Min Vertex Cover. Our experimental results for various benchmarks are superior to all approaches reported earlier. 1
Generic ILP versus Specialized 01 ILP: An Update
 IN INTERNATIONAL CONFERENCE ON COMPUTERAIDED DESIGN
, 2002
"... Optimized solvers for the Boolean Satisfiability (SAT) problem have many applications in areas such as hardware and software verification, FPGA routing, planning, etc. Further uses are complicated by the need to express "counting constraints" in conjunctive normal form (CNF). Expressing such constra ..."
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Cited by 77 (21 self)
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Optimized solvers for the Boolean Satisfiability (SAT) problem have many applications in areas such as hardware and software verification, FPGA routing, planning, etc. Further uses are complicated by the need to express "counting constraints" in conjunctive normal form (CNF). Expressing such constraints by pure CNF leads to more complex SAT instances. Alternatively, those constraints can be handled by Integer Linear Programming (ILP), but generic ILP solvers may ignore the Boolean nature of 01 variables. Therefore specialized 01 ILP solvers extend SAT solvers to handle these socalled "pseudoBoolean" constraints. This work
Solving MaxSAT as weighted CSP
, 2003
"... For the last ten years, a significant amount of work in the constraint community has been devoted to the improvement of complete methods for solving soft constraints networks. We wanted to see how recent progress in the weighted CSP (WCSP) field could compete with other approaches in related fie ..."
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Cited by 44 (11 self)
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For the last ten years, a significant amount of work in the constraint community has been devoted to the improvement of complete methods for solving soft constraints networks. We wanted to see how recent progress in the weighted CSP (WCSP) field could compete with other approaches in related fields.
AMUSE: A MinimallyUnsatisfiable Subformula Extractor
, 2004
"... This paper describes a new algorithm for extracting unsatisfiable subformulas from a given unsatisfiable CNF formula. Such unsatisfiable “cores ” can be very helpful in diagnosing the causes of infeasibility in large systems. Our algorithm is unique in that it adapts the “learning process ” of a mod ..."
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Cited by 32 (5 self)
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This paper describes a new algorithm for extracting unsatisfiable subformulas from a given unsatisfiable CNF formula. Such unsatisfiable “cores ” can be very helpful in diagnosing the causes of infeasibility in large systems. Our algorithm is unique in that it adapts the “learning process ” of a modern SAT solver to identify unsatisfiable subformulas rather than search for satisfying assignments. Compared to existing approaches, this method can be viewed as a bottomup core extraction procedure which can be very competitive when the core sizes are much smaller than the original formula size. Repeated runs of the algorithm with different branching orders yield different cores. We present experimental results on a suite of large automotive benchmarks showing the performance of the algorithm and highlighting its ability to locate not just one but several cores.
Leakage Current Reduction in CMOS VLSI Circuits by Input Vector Control
, 2004
"... The first part of this paper describes two runtime mechanisms for reducing the leakage current of a CMOS circuit. In both cases, it is assumed that the system or environment produces a "sleep" signal that can be used to indicate that the circuit is in a standby mode. In the first method, the "sleep" ..."
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Cited by 27 (4 self)
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The first part of this paper describes two runtime mechanisms for reducing the leakage current of a CMOS circuit. In both cases, it is assumed that the system or environment produces a "sleep" signal that can be used to indicate that the circuit is in a standby mode. In the first method, the "sleep" signal is used to shift in a new set of external inputs and preselected internal signals into the circuit with the goal of setting the logic values of all of the internal signals so as to minimize the total leakage current in the circuit. This minimization is possible because the leakage current of a CMOS gate is strongly dependent on the input combination applied to its inputs. In the second method, NMOS and PMOS transistors are added to some of the gates in the circuit to increase the controllability of the internal signals of the circuit and decrease the leakage current of the gates using the "stack effect". This is, however, done carefully so that the minimum leakage is achieved subject to a delay constraint for all inputoutput paths in the circuit. In both cases, Boolean satisfiability is used to formulate the problems, which are subsequently solved by employing a highly efficient SAT solver. Experimental results on the combinational circuits in the MCNC91 benchmark suite demonstrate that it is possible to reduce the leakage current in combinational circuits by an average of 25% with only 5% delay penalty. The second part of this paper presents a design technique for applying the minimum leakage input to a sequential circuit. The proposed method uses the builtin scanchains in a VLSI circuit to drive it with the minimum leakage vector when it enters the sleep mode. The use of these scan registers eliminates the area and delay overhead of the additional circuitry ...
An analysis of SATbased model checking techniques in an industrial environment
 In CHARME
, 2005
"... ..."
Robust SATBased Search Algorithm for Leakage Power Reduction
, 2002
"... Leakage current promises to be a major contributor to power dissipation in future technologies. Bounding the maximum and minimum leakage current poses an important problem. Determining the maximum leakage ensures that the chip meets power dissipation constraints. Applying an input pattern that minim ..."
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Cited by 24 (12 self)
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Leakage current promises to be a major contributor to power dissipation in future technologies. Bounding the maximum and minimum leakage current poses an important problem. Determining the maximum leakage ensures that the chip meets power dissipation constraints. Applying an input pattern that minimizes leakage allows extending battery life when the circuit is in standby mode. Finding such vectors can be expressed as a satisfiability problem. We apply in this paper an incremental SAT solver, PBS [1], to find the minimum or maximum leakage current. The solver is called as a postprocess to a randomvectorgeneration approach. Our results indicate that using a such a generic SAT solver can improve on previously proposed random approaches [7].
Randomised Backtracking for Linear PseudoBoolean Constraint Problems
, 2002
"... Many constraint satisfaction and optimisation problems can be expressed using linear constraints on pseudoBoolean (0/1) variables. Problems expressed in this form are usually solved by integer programming techniques, but good results have also been obtained using generalisations of SAT algorithm ..."
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Cited by 22 (9 self)
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Many constraint satisfaction and optimisation problems can be expressed using linear constraints on pseudoBoolean (0/1) variables. Problems expressed in this form are usually solved by integer programming techniques, but good results have also been obtained using generalisations of SAT algorithms based on both backtracking and local search. A recent class of algorithm uses randomised backtracking to combine constraint propagation with local searchlike scalability, at the cost of completeness. This paper describes such an algorithm for linear pseudoBoolean constraint problems. In experiments it compares well with stateoftheart algorithms on hardware verification and balanced incomplete block design generation, and finds improved solutions for three instances of the Social Golfer Problem.
Incremental and complete bounded model checking for full PLTL
 In CAV’05, volume 3576 of LNCS
, 2005
"... Abstract. Bounded model checking is an efficient method for finding bugs in system designs. The major drawback of the basic method is that it cannot prove properties, only disprove them. Recently, some progress has been made towards proving properties of LTL. We present an incremental and complete b ..."
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Cited by 18 (4 self)
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Abstract. Bounded model checking is an efficient method for finding bugs in system designs. The major drawback of the basic method is that it cannot prove properties, only disprove them. Recently, some progress has been made towards proving properties of LTL. We present an incremental and complete bounded model checking method for the full linear temporal logic with past (PLTL). Compared to previous works, our method both improves and extends current results in many ways: (i) our encoding is incremental, resulting in improvements in performance, (ii) we can prove nonexistence of a counterexample at shallower depths in many cases, and (iii) we support full PLTL. We have implemented our method in the NuSMV2 model checker and report encouraging experimental results.
SymmetryBreaking for PseudoBoolean Formulas
, 2003
"... Many important tasks in circuit design and verification can be performed in practice via reductions to Boolean Satisfiability (SAT), making SAT a fundamental EDA problem. However such reductions often leave out applicationspecific structure, thus handicapping EDA tools in their competition with cre ..."
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Cited by 15 (9 self)
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Many important tasks in circuit design and verification can be performed in practice via reductions to Boolean Satisfiability (SAT), making SAT a fundamental EDA problem. However such reductions often leave out applicationspecific structure, thus handicapping EDA tools in their competition with creative engineers. Successful attempts to represent and utilize additional structure on Boolean variables include recent work on 01 Integer Linear Programming (ILP) and on symmetries in SAT. Those extensions gracefully...