We present an approach for formal verification of the DC and low frequency behavior of synthesized analog designs containing linear components and components whose behavior can be represented by piecewise linear models. A formal model of the structural description of a synthesized design is extracted from the sized component netlist produced by the synthesis tool, in terms of characteristic behavior of the components and various voltage and current laws. For the synthesized implementation to be correct, it must imply a formal model extracted from a user given behavior specification. Circuit implementation and expected behavior are both modeled in the PVS higher-order logic proof checker as linear functions and the PVS decision procedures are used to prove the implication. 1 Introduction The challenges in formally verifying an analog design are some what different from those in verifying digital designs. Analog components exhibit continuous time behavior often represented as an...

In this paper, we present a methodology for rapid prototyping of linear time-invariant analog systems. The prototyping hardware is composed of field-programmable analog arrays (FPAAs) to enable rapid evaluation and validation of analog designs. Starting with a signal flow graph description of the system, a library-based technology mapping phase produces FPAA designs optimized for area. The technology mapper then explores the design space by performing gain distribution. Technology mapping is followed by the placement and routing phase that generates the physical layout on the target single-segment array-based FPAA architecture. We employ an integrated place and route approach in order to guarantee routability and performance. 1. Introduction The VHDL-AMS Synthesis Environment (VASE) being developed at the University of Cincinnati performs synthesis of analog designs from specifications in VHDLAMS [1]. Rapid prototyping of these designs using fieldprogrammable analog arrays (FPAAs) en...

In this paper, we present a rapid prototyping environment for mixed signal systems. The environment consists of programmable mixed signal hardware together with a set of integrated CAD tools to enable fast prototyping of mixed signal designs from high-level specifications. The prototyping hardware comprises of field-programmable analog arrays and field-programmable gate arrays on which the analog and digital sections of the design are respectively implemented. Field-programmable interconnect routes signals between multiple devices. A bank of data converters constitutes the interface between the analog and digital parts. Design tools are required to map the given design onto the prototyping hardware. The high-level design specification is first compiled into an intermediate format suitable for synthesis. Following this, the design is partitioned into analog and digital sections. The analog and digital subsystems are synthesized for the target FPAA and FPGA devices respectively. Configur...

In this paper, we present a methodology to synthesize CMOS RF devices from high-level circuit specifications into transistor netlists. The core of the methodology is an estimator of RF analog CMOS circuits, which evaluates the performance parameters of various circuit topologies. The estimation engine is based on a hierarchical analog performance estimator and a set of heuristics. The synthesis environment considers all performance parameters into account, and it relies on a genetic algorithm based heuristic method to search for a solution in a large design-space. The synthesis tool determines a solution set of design parameters such that the RF circuit satisfies the overall design constraints. 1.

Session 2 Mixed-signal modeling Modeling and simulation of a Sigma-Delta digital to analog converter using VHDL-AMS

Rapid prototyping followed by technology retargeting provides a fast and cost-effective approach to analog system synthesis. Field-programmable analog arrays (FPAAs) enable rapid implementation of a function-compliant prototype, while technology retargeting converts the functional FPAA prototype to an ASIC. We first address the FPAA technology mapping problem. A novel structural approach based on hierarchical pattern matching and covering is employed to map the analog behavior onto the FPAA. We then address issues of technology retargeting and design reuse, and present our FPAA-ASIC retargeting strategy. We present experiments and a design example for FPAA technology mapping and retargeting.