This paper presents resource and latency constrained scheduling algorithms to minimize power/energy consumption when the resources operate at multiple voltages (5 V, 3.3 V, 2.4 V, and 1.5 V). The proposed algorithms are based on efficient distribution of slack among the nodes in the data-flow graph. The distribution procedure tries to implement the minimum energy relation derived using the Lagrange multiplier method in an iterative fashion. Two algorithms are proposed, 1) a low complexity ( ) algorithm and 2) a high complexity ( log( )) algorithm, where is the number of nodes and is the latency. Experiments with some HLS benchmark examples show that the proposed algorithms achieve significant power/energy reduction. For instance, when the latency constraint is 1.5 times the critical path delay, the average reduction is 39%.

Abstract—This paper presents a resource-constrained scheduling scheme and a latency-constrained scheduling scheme that minimize power consumption for the case when the resources operate at multiple voltages. The resource-constrained scheduling reduces the power consumption by maximally utilizing resources operating at reduced voltages and, at the same time, reducing the latency. The latency-constrained scheduling scheme reduces the power consumption by assigning as many nodes (of the data flow graph) as possible to the resources operating at reduced voltages. Both schemes consider the effect of switching activity on the power consumption of the functional units. In addition, both schemes use heuristics to reduce the power consumed by the level shifters. Experiments with HLS benchmark examples show that the proposed schemes achieve significant power reduction when the operating voltages are 5 and 3.3 V or 5, 3.3, and 2.4 V. Index Terms—Behavioral synthesis, latency-constrained scheduling, low-power design, multiple voltage scheduling, resource-constrained scheduling. I.

In this paper, we propose an energy efficient synthesis technique for datapath circuits. Specifically, we propose a time and resource constrained scheduling algorithm, (DFMVS), which utilizes the concept of Dynamic Frequency Clocking and Multiple Voltage Scaling. In the dynamic frequency scheme, all units are driven by a single clock line which changes at run time depending on the functional unit active at that time. Recently, the use of multiple voltages has been investigated in the context of energy minimization. DFMVS consists of two modules: Dynamic_freq_sched and Modify_sched. Based on the dynamic frequency scheme, Dynamic_freq_sched generates an initial schedule in which the control steps are clocked at different frequencies. Modify_sched incorporates a schedule modifier, that regroups the operations of the initial schedule such that multiple voltages can be used to reduce the energy consumption. The algorithm has been applied to various high level synthesis benchmark circuits under different time and resource constraints. The experimental results show that using three supply voltage levels (5.0V, 3.3V, 2.4V), an average energy saving of 53.5 % (with the time constraint of 2.0 times the critical path) is obtained as compared to using a uni-frequency clocking scheme with a single supply voltage.

In this paper, we tackle the problem of peak and average power optimization in high-level synthesis. Because of the quadratic relationship of supply-voltage to the dynamic power consumption, voltage scaling is considered as the most efficient technique for reducing power consumptions in CMOS circuits. We present an MILP formulation for the scheduling problem using multiple supply-voltages in order to optimize peak power as well as average power and energy consumptions. As the design problem becomes large, exact solution takes a tremendous amount of run-time; and to explore the design space in a reasonable amount of time, a high quality heuristic is needed. Thus, we devise a two-phase heuristic to solve the multiple supply-voltages scheduling for peak and average power minimization. In the first phase, a guided LP relaxation is developed. Following the relaxed LP schedule, a power-area-saving procedure is developed. Results for peak and average power of our two-phase heuristic well match those obtained by the optimal solution as has been validated through extensive experiments on several benchmarks. I.

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