Reconfigurable hardware has been shown to provide an efficient compromise between the flexibility of software and the performance of hardware. However, even coarse-grained reconfigurable architectures target the general case, and miss optimization opportunities present if characteristics of the desired application set are known. We can therefore increase efficiency by restricting the structure to support a class or a specific set of algorithms, while still providing flexibility within that set. By generating a custom array for a given computation domain, we explore the design space between an ASIC and an FPGA.

In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs). For simplicity of reference, we simply refer to these devices as FPGAs. First, we capture the relationship between FPGA power dissipation and I/O signal statistics. We then use an adaptive regression method to model the FPGA power consumption. Such a high-level model can be used in the inner loop of a system-level synthesis tool to estimate the power consumed by different FPGA resources for different potential system-level synthesis solutions. It can also be used to verify the power budgets during embedded system design. With our high-level power model, the FPGA power consumption can be obtained very quickly. Experimental results indicate that the average relative error is only 3.1 % compared to low-level FPGA power simulation methods. 1.

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In this paper we propose a new architecture for general-purpose computing which combines a reconfigurable-hardware substrate and compiler technology to generate Application-Specific Hardware (ASH). The novelty of this architecture is that resources are not shared: each different static program instruction can have its own dedicated hardware implementation. ASH enables the synthesis of circuits with only local computation structures, which promise to be fast, inexpensive and use very little power. This paper also presents a scalable compiler framework for ASH, which generates hardware from programs written in C and some evaluations of the resources necessary for implementing realistic programs.

This work presents the architecture of PROSIDIS, a special purpose processor designed to search for the occurrence of substrings similar to a given `template string' within a proteome.

Reconfigurable Computing (RC) is a technology that makes use of programmable logic (FPGAs) in conjunction with a traditional microprocessor to accelerate generalpurpose applications. Although the hardware resources in current FPGA devices are rapidly growing, a full-sized application will completely overwhelm even the largest available device. Consequently, only a portion of the application can be accelerated by the reconfigurable resources, and determining the optimal portion to map is difficult in practice and undecidable in general. But, because FPGAs are reconfigurable, researchers are investigating Run-Time Reconfigurable (RTR) systems which allow the FPGA to be reconfigured while the application is running. These novel architectures exploit the individual strengths of hardware and software by allowing the architecture to execute parts of a program in software and other parts in hardware. In this project we investigate how to translate and execute Java applications on an online RTR architecture. 1.

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The integration of methodologies and techniques from parallel processing or High Performance Computing (HPC) with those of Reconfigurable Computing (RC) systems offers great potential for increased performance and flexibility for a wide range of computing problems. High Performance Computing architectures and Reconfigurable Computing systems have independently demonstrated performance advantages for applications such as digital signal processing, circuit simulation, and pattern recognition. By exploiting the near “hardware specific ” speed of Reconfigurable Computing systems in a Beowolf cluster there is potential for significant performance advantages over other software-only or uniprocessor solutions. In this paper we present our initial results for an analytical modeling framework for High Performance Reconfigurable Computing systems.

This paper presents an easy procedure to develop a reconfigurable application in a Virtuoso real-time operating system using the visual environment TEV developed at DC/UFSCar. In TEV, applications are built using graphs, where nodes are data structures that compose a parallel program (tasks, signals, resources, mailboxes, etc.), and arrows denote the communication and synchronization operations between the data structures. The information in the graphical model can be complemented with code written by the user. Based on this construction, the source code of the application is automatically generated. This work describes a proposal of the TEV extension with reconfigurable applications, denoting R-TEV, using a reconfigurable functions library. A case study is presented, using three reconfigurable functions, and the results show that the proposal is feasible. 1.

Reconfigurable hardware has been shown to provide an efficient compromise between the flexibility of software and the performance of hardware. However, even coarse-grained reconfigurable architectures target the general case, and miss optimization opportunities present if characteristics of the desired application set are known. We can therefore increase efficiency by restricting the structure to support a class or a specific set of algorithms, while still providing flexibility within that set. By generating a custom array for a given computation domain, we explore the design space between an ASIC and an FPGA.