Results 1  10
of
41
Automatic verification of finitestate concurrent systems using temporal logic specifications
 ACM Transactions on Programming Languages and Systems
, 1986
"... We give an efficient procedure for verifying that a finitestate concurrent system meets a specification expressed in a (propositional, branchingtime) temporal logic. Our algorithm has complexity linear in both the size of the specification and the size of the global state graph for the concurrent ..."
Abstract

Cited by 1194 (58 self)
 Add to MetaCart
We give an efficient procedure for verifying that a finitestate concurrent system meets a specification expressed in a (propositional, branchingtime) temporal logic. Our algorithm has complexity linear in both the size of the specification and the size of the global state graph for the concurrent system. We also show how this approach can be adapted to handle fairness. We argue that our technique can provide a practical alternative to manual proof construction or use of a mechanical theorem prover for verifying many finitestate concurrent systems. Experimental results show that state machines with several hundred states can be checked in a matter of seconds.
Protocol Verification as a Hardware Design Aid
 IN IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS
, 1992
"... The role of automatic formal protocol verification in hardware design is considered. Principles are identified that maximize the benefits of protocol verification while minimizing the labor and computation required. A new protocol description language and verifier (both called Mur') are descri ..."
Abstract

Cited by 233 (27 self)
 Add to MetaCart
The role of automatic formal protocol verification in hardware design is considered. Principles are identified that maximize the benefits of protocol verification while minimizing the labor and computation required. A new protocol description language and verifier (both called Mur') are described, along with experiences in applying them to two industrial protocols that were developed as part of hardware designs.
Better Verification Through Symmetry
, 1996
"... A fundamental difficulty in automatic formal verification of finitestate systems is the state explosion problem  even relatively simple systems can produce very large state spaces, causing great difficulties for methods that rely on explicit state enumeration. We address the problem by exploiting ..."
Abstract

Cited by 187 (8 self)
 Add to MetaCart
A fundamental difficulty in automatic formal verification of finitestate systems is the state explosion problem  even relatively simple systems can produce very large state spaces, causing great difficulties for methods that rely on explicit state enumeration. We address the problem by exploiting structural symmetries in the description of the system to be verified. We make symmetries easy to detect by introducing a new data type scalarset, a finite and unordered set, to our description language. The operations on scalarsets are restricted so that states are guaranteed to have the same future behaviors, up to permutation of the elements of the scalarsets. Using the symmetries implied by scalarsets, a verifier can automatically generate a reduced state space, on the fly. We provide a proof of the soundness of the new symmetrybased verification algorithm based on a definition of the formal semantics of a simple description language with scalarsets. The algorithm has been implemented ...
An Improved Protocol Reachability Analysis Technique
 SOFTWARE, PRACTICE AND EXPERIENCE
, 1988
"... An automated analysis of all reachable states in a distributed system can be used to trace obscure logical errors that would be very hard to find manually. This type of validation is traditionally performed by the symbolic execution of a finite state machine (FSM) model of the system studied. The ..."
Abstract

Cited by 52 (13 self)
 Add to MetaCart
An automated analysis of all reachable states in a distributed system can be used to trace obscure logical errors that would be very hard to find manually. This type of validation is traditionally performed by the symbolic execution of a finite state machine (FSM) model of the system studied. The application
Verifying Systems with Replicated Components in Murφ
, 1997
"... An extension to the Murphi verifier is presented to verify systems with replicated identical components. Although most systems are finitestate in nature, many of them are also designed to be scalable, so that a description gives a family of systems, each member of which has a different number of re ..."
Abstract

Cited by 43 (3 self)
 Add to MetaCart
An extension to the Murphi verifier is presented to verify systems with replicated identical components. Although most systems are finitestate in nature, many of them are also designed to be scalable, so that a description gives a family of systems, each member of which has a different number of replicated components. It is therefore desirable to be able to verify the entire family of systems, independent of the exact number of replicated components. The verification is performed by explicit state enumeration in an abstract state space where states do not record the exact numbers of components. We provide an extension to the existing Murphi language, by which a designer can easily specify a system in its concrete form. Through a new datatype, called RepetitiveID, a designer can suggest the use of this abstraction to verify a family of systems. First of all, Murphi automatically checks the soundness of this abstraction. Then it automatically translates the system description to an abstract ...
On limits and possibilities of automated protocols analysis
 in IFIP WG6.1 7th. Int. Conf on Proto col Specification, Testing and Verification
, 1987
"... ..."
Deriving protocol specifications from service specifications
 In Communications, Architectures & Protocols, Proceedings of the ACM SIGCOMM ‘86 Symposium. ACM
, 1986
"... The service specification concept has acquired an increasing level of recognition by protocol designers. This architectural concept influences the methodology applied to service and protocol definition. Since the protocol is seen as the logical implementation of the service, one can ask whether it i ..."
Abstract

Cited by 18 (9 self)
 Add to MetaCart
The service specification concept has acquired an increasing level of recognition by protocol designers. This architectural concept influences the methodology applied to service and protocol definition. Since the protocol is seen as the logical implementation of the service, one can ask whether it is possible to formally derive the specification of a protocol providing a given service. This paper addresses this question and presents an algorithm for deriving a protocol specification from a given service specification. It is assumed that services are described by expressions, where names identifying both service primitives and previously defined services are composed using operators for sequence, parallelism and alternative. Services and service primitives may have input and output parameters. Composition of services from predefined services and service primitives is also permitted. The expression defining the service is the basis for the protocol derivation process. The algorithm presented fully automates the derivation process. Future work will focus on the optimization of traffic between protocol entities and on applications.
Specification of a simplified Transport Protocol Using Different Formal Description Techniques
 Comput. Networks ISDN Systems
"... Ddpartement d'informatique et de recherche opdrationnelle, Universitd ..."
Abstract

Cited by 14 (5 self)
 Add to MetaCart
Ddpartement d'informatique et de recherche opdrationnelle, Universitd
Formal Verification of Complex Coherence Protocols Using Symbolic State Models
, 1995
"... Directorybased coherence protocols are so complex that verification techniques based on automated procedures are required to establish their correctness. State enumeration approaches are wellsuited to the verification of cache protocols but they face the problem of state space explosion, leading t ..."
Abstract

Cited by 11 (2 self)
 Add to MetaCart
Directorybased coherence protocols are so complex that verification techniques based on automated procedures are required to establish their correctness. State enumeration approaches are wellsuited to the verification of cache protocols but they face the problem of state space explosion, leading to unacceptable verification time and memory consumption even for very small system configurations. In our previous work, we have introduced a verification methodology based on a symbolic state model of the system to verify. In this study, we apply this methodology to a writeinvalidate, fullmap directorybased coherence protocol for nonFIFO interconnection networks i.e. networks in which the order of messages between two nodes is not preserved from source to destination. We develop the concepts and notations to verify some properties of the protocol with a symbolic state model (SSM). We compare the verification with SSM to the verification with the Stanford Murj system and show that SSM i...
On Test Case Generation From Asynchronously Communicating State Machines
, 1997
"... This paper proposes an approach for generating test cases in Concurrent TTCN from a system of asynchronously communicating finite state machines. We give an algorithm for generating a noninterleaving model of prime event structures from a generalized model of asynchronously communicating finite stat ..."
Abstract

Cited by 7 (1 self)
 Add to MetaCart
This paper proposes an approach for generating test cases in Concurrent TTCN from a system of asynchronously communicating finite state machines. We give an algorithm for generating a noninterleaving model of prime event structures from a generalized model of asynchronously communicating finite state machines and deal with the generation of test cases from prime event structures.