We present a framework for high-level synthesis that enables the designer to explore the best choice of source level and low level parallelizing transformations for improved synthesis. Within this framework, we have implemented a methodology that applies a set of parallelizing code transformations, both at the source level and during scheduling. Using these transformations, the designer can optimize high-level synthesis results and reduce the impact of control flow constructs on the quality of results. In our methodology, we first apply a set of source level pre-synthesis transformations that include common sub-expression elimination (CSE), copy propagation, dead code elimination and loop-invariant code motion, along with more coarse level code restructuring transformations such as loop unrolling. We then explore scheduling techniques that use a set of aggressive speculative code motions to maximally parallelize the design by re-ordering, speculating and sometimes even duplicating operations in the design. In particular, we present a new technique called "Dynamic CSE" that dynamically coordinates CSE and code motions such as speculation and conditional speculation during scheduling. We also show how operation chaining across conditional boundaries can be used to optimize control flow. We have built the Spark high-level synthesis framework that takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. Our results from three moderately complex design targets, namely, MPEG-1, MPEG-2 and the GIMP image processing tool validate the utility of our approach to the behavioral synthesis of designs with complex control flows.

Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most of the existing behavior-level scheduling heuristics either have a limited efficiency in a specific class of applications or lack general support of various design constraints. In this

The quality of synthesis results for most high level synthesis approaches is strongly affected by the choice of control flow (through conditions and loops) in the input description. This leads to a need for high-level and compiler transformations that overcome the effects of syntactic variance or programming style on the quality of generated circuits. To address this issue, we have developed a set of speculative code motion transformations that enable movement of operations through, beyond, and into conditionals with the objective of maximizing performance. We evaluate the effects of these speculative code motions in terms of the cycles on the longest path (performance), the number of states in the finite state machine (FSM) (controller complexity), length of the critical path in the synthesized netlist (clock period) and the area of the synthesized netlist. Significant improvements in performance and reduction in controller complexity are observed. However, although critical path lengths remain fairly constant, area of the design increases due to increasing complexity of the steering logic and associated control logic. To address this, we present a methodology to reduce interconnections based on resource binding, which also leads to improvements in critical path lengths. These code transformations and controller optimizations have been implemented in a high-level synthesis research framework called Spark, which takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. The experiments described in this paper have been performed on two real-life high-level synthesis design targets, namely, the MPEG-1 and ADPCM algorithms. The results demonstrate reductions in the number of states in the FSM controller and in the cycles on...

This paper describes a practical technique for the optimal scheduling of control dominated systems minimizing the weighted average latency over all control branches. Such a weighted metric is crucial for control dependent scheduling to accommodate practical architectural goals. In contrast to most weighting mechanisms, a non-Bayesian probabilistic measure is used to avoid assumptions of branch independence. The underlying scheduling model allows general FSM-based models for operations, captures several forms of speculative execution and scales well with increasing control complexity.

A number of researchers have proposed the use of Boolean satisfiability solvers for verifying C programs. They encode correctness checks as Boolean formulas using finitization: loops and recursion are bounded, as is the size of the input instances. The SAT approach has been shown to find subtle bugs with reasonable resources. However, it does not scale well; in particular, it lacks the ability to handle larger bounds. We present SEBAC, which can handle the same class of programs as the SAT approach, and scales to bounds that are orders of magnitude higher. The key difference between SEBAC and SAT techniques is SEBAC’s use of imperative Boolean sequential circuits, which are Boolean formulas with memory elements instead of the Boolean formulas which are stateless.

Scheduling, or planning, is widely recognized as a very important step in several domains such as high level synthesis, real-time systems, and every-day applications. Given a problem described by a number of actions and their relationships, finding a schedule, or a plan, means to find a way to perform all the actions minimizing a specific cost function. The goal of this paper is to develop, analyze and compare different scheduling techniques on a new scheduling/planning problem. The new application domain is aircraft maintenance. It shares with previous ones the underlying problem definition, but it also unveils brand new challenging characteristics, and a different optimization target. We show how to model the problem in a suitable way, and how to solve it with different methodologies going from Satisfiability solvers and Binary Decision Diagrams, to Timed Automata and Coloured Petri Nets. New ideas are put forward in the different domains having efficiency and scalability as main targets. Experimental results stress the different techniques, showing their application range and limits, and defining advantages and disadvantages of the underlying models. Overall, general-purpose tools have been easily applied to our problem, but failed as far as efficiency was concerned. The satisfiability-based approach proved to be faster and more scalable, being able to solve instances 3 − 4 times larger. To sum up, our contributions range from modeling the aircraft maintenance problem as a scheduling instance, to coding this problem with home-made and general-purpose tools, to dovetailing exact and heuristic techniques, and comparing these techniques in terms of efficiency and scalability. Keywords: planning Boolean satisfiability, SAT-solvers, timed automata, Petri nets, scheduling,