Abstract. We propose a mathematical framework to deal with the composition of heterogeneous reactive systems. Our theory allows to establish theorems, from which design techniques can be derived. We illustrate this by two cases: the deployment of synchronous designs over GALS architectures, and the deployment of synchronous designs over the so-called Loosely Time-Triggered Architectures. 1

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Rapid growth in the c,15552,( ofsystem-on-c94, is being acng,29063 byinc easing volume and diversity ofon-c31 c-c316 ccc trafficff,79 in turn,is driving the development of advanc2 system-level c058,(56100, arc,14521, es. While these arc,23587, es have the potential to improve system performanc99,(5 pose significni new cw,29066, to the system designer,owing to thece,200 designspac defined by the availability of numerous networktopologies,c12,c12,c protoc7,(525 mapping alternatives for systemctem,20373,(52 In this paper,we address the problem of mapping a system'sctem's,23426 requirements to a given c3095,(50724 arc,20263, e template. We illustrate the nature of the c,13740,(498 arc,20611, e design spacn anddesc245 an exploration methodology that uses effic,23 algorithms to help automate the proc12 of mapping the system ctem,23084,(4 to theselec90 template. In addition,we demonstrate the importanc of simultaneously optimizing theon-c57 cc5707,(462 protoc63 in order to maximize system performanc6 Experimentscxperime on example systems,inc(4444 ac14 forwarding unit of an ATMswitc8 indic8 that the proposedtecd,1319 aid inautomatic354 ctomatic35 ctomatic35 arc10172,( es that have high performanc4 For the systems wec,4889, ed,the solutions generated using our methodology had 53% superior performanc (on average),over those based on c, ventional arc,4712,( es and mapping approac,15 The algorithms used in the proposed methodology arec3130,(39065,c effic20107,( sc2 well with inc easing cing,7446,(3 arc,13897, ec7281,(38 .

Abstract—Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few application-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and a major improvement in the achievable network through with minimal impact on network topology. Index Terms—Design automation, multiprocessor system-onchip (MP-SoC), network-on-chip (NoC), performance analysis. I.

In this paper we introduce the notion of weak endochrony, which extends to a synchronous setting the classical theory of Mazurkiewicz traces. The notion is useful in the synthesis of correct-by-construction communication protocols for globally asynchronous, locally synchronous (GALS) systems. The independence between various computations can be exploited here to provide communication schemes that do not restrict concurrency while still guaranteeing correctness. 1.

Synchronous systems offer a clean semantics and an easy verification path at the expense of often inefficient implementations. Capturing design specifications as synchronous models and then implementing the specifications in a less restrictive platform allow to address a much larger design space. The key issue in this approach is maintaining semantic equivalence between the synchronous model and its implementation. We address this problem by showing how to map a synchronous model onto a loosely timetriggered architecture that is fairly straightforward to implement as it does not require global synchronization or blocking communication. We show how to maintain semantic equivalence between specification and implementation using an intermediate model (similar to a Kahn process network but with finite queues) that helps in defining the transformation. Performance of the semantic preserving implementation is studied for the general case as well as for a few special cases. 1

This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in the physical design stage. It can be shown that proper queue sizing can reduce or even completely avoid the performance loss due to imbalanced relay stations insertion in reconvergent paths. Moreover, the problem of queue sizing and placement of the additional buffers for maximum performance is formulated and studied to properly allocate available chip areas in the layout to communication channels. An algorithm based on mixed integer linear programming is proposed. Experimental results show that queue sizing is effective in improving the performance of latency insensitive systems even under tight area constraints. Moreover, the proposed algorithm is sufficiently efficient in obtaining the optimal solution for systems of practical sizes. 1.

We present a compositional theory of heterogeneous reactive systems. The approach is based on the concept of tags marking the events of the signals of a system. Tags can be used for multiple purposes from indexing evolution in time (time stamping) to expressing relations among signals like coordination (e.g., synchrony and asynchrony), and causal dependencies. The theory provides flexibility in system modeling because it can be used both as a unifying mathematical framework to relate heterogeneous models of computations and as a formal vehicle to implement complex systems by combining heterogeneous components. In particular, we introduce an algebra of tag structures to define heterogeneous parallel composition formally. Morphisms between tag structures are used to define relationships between heterogeneous models at different levels of abstraction. In particular, they can be used to represent design transformations from tightly-synchronized specifications to loosely-synchronized implementations. The theory has an important application in the correct-by-construction deployment of synchronous design on distributed architectures.

Back-pressure is a logical mechanism to control the flow of information on a communication channel of a latency-insensitive system (LIS) while guaranteeing that no packet is lost. Back-pressure is necessary for building open LISs and it represents an interesting design alternative also for closed LISs because it makes possible to realize highly modular implementations with more predictable features in terms of design overhead (area, power). In discussing the role of back-pressure, we revisit the logic of the necessary building blocks, and explain the impact of the system topology on the system performance.

Abstract—This paper formally models and studies latencyinsensitive systems (LISs) through max-plus algebra. We introduce state traces to model behaviors of LISs and obtain a formally proved performance upper bound achievable by latencyinsensitive design. An implementation of the latency-insensitive protocol that can provide robust communication through backpressure is also proposed. The intrinsic performance of the proposed implementation is acquired based on state traces. It is also proved that the proposed implementation can always reach the best performance achievable by latency-insensitive design. Index Terms—Back-pressure, latency-insensitive system, maxplus algebra, performance analysis, state trace.