A discrete event simulation model may contain several events with the same timestamp, referred to as simultaneous events. The order of execution of such events may affect the outcome of the simulation. Simulation systems and protocols use different, often ad-hoc, tie-breaking mechanisms to order simultaneous events. As a result, it may be impossible to reproduce the results of a simulation model across different simulators. In this paper we define two tie-breaking mechanisms- arbitrary, which allows a non-deterministic ordering of simultaneous events, and user-consistent which produces a deterministic execution based on simultaneous event orderings specified by the user. The latter requires that the user defined simultaneous event ordering rules be consistent, and if followed, must result in a unique execution. We specify sufficient conditions under which such a guarantee can be made. We show that for some simulation protocols, the ability to enforce a particular tie-breaking mechanism...

In the last three decades a considerable amount of research has been pursued in the efficient implementation of the pending event set (PES) associated with discrete-event simulation. The reason is simple: a fast event management has a very crucial impact in the total running time of both sequential and parallel simulations. This report focuses on this problem by studying the empirical performance of a number of solutions to the PES implementation in which we include a complete binary tree described in [26], 1 Introduction The PES is defined as the set of all the events generated during a discrete-event simulation and whose occurrence have not been simulated yet. In order to determine the next event to take place, it is necessary to extract the event with the least time from the PES. We call this operation extract-min. On the other hand, the occurrence of any event during the simulation can produce the insertion of new pending or future events in the PES; insert operation. These two b...

this paper we study the performance of the very first tournament based complete binary tree. We focus on discrete-event simulation and our results show that this unknown predecessor of heaps can be a more efficient alternative to the fastest pending event set implementations reported in the literature. We also extend the idea of binary tournaments to a (2; L)-tournament structure which exhibits the property of delaying the processing of events with larger timestamps whilst it keeps similar theoretical performance bounds to the native (2; 1)-structure or CBT. This property can be certainly useful in systems where many pending events are expected to be deleted or rescheduled during the simulation. 2 Tournament trees

The bulk-synchronous parallel (BSP) model of computing has been proposed to enable the development of portable software which achieves scalable performance across diverse parallel architectures. A number of applications of computing science have been demonstrated to be efficiently supported by the BSP model in practice.

We present a new approach to speeding up VHDL simulation. In this approach, the simulation code is generated with routines for unused VHDL features stripped off. The VHDL simulator optimized in this way runs faster when the design is described mostly with simple constructs and expressions. We prepare multiple functions for each task in the simulation process. Each function is pre-optimized for each possible case. When a design is compiled and the simulation code is generated, we select functions that best fit with the design. With this approach and with several other optimization techniques, we obtained about twofold speedup. 1 Introduction VHDL is now a very popular language used to design a system with top-down design methodology. There are many VHDL simulators provided by many vendors and we need to choose one that best fits with our purpose. One of the major consideration in choosing a simulator is the simulation speed. As a matter of fact, the time taken by simulation occupies a...

LECSIM is a highly efficient logic simulator which integrates the advantages of event driven interpretive simulation and levelized compiled simulation. Two techniques contribute to the high efficiency. First it employs the zero-delay simulation model with levelized event scheduling to eliminate most unnecessary evaluations. Second, it compiles the central event scheduler into simple local scheduling segments which reduces the overhead of event scheduling. Experimental results show that LECSIM runs about 8-77 time faster than traditional unit-delay event-driven interpretive simulator. LECSIM also provides the option of scheduling with respect to individual gates or with respect to fan-out free blocks. When the circuit is partitioned into fan-out free blocks, the speed increases by a factor of 2-3. With partitioning, the speed of LECSIM is only about 1.5-3.4 times slower than a levelized compiled simulation.

Compilation, Synthesis, and Simulation of Hardware Description Languages --- The Compositional Models of HDL's by Szu-Tsung Cheng Doctor of Philosophy in Computer Science University of California, Berkeley Professor Robert K. Brayton, Chair With the advent of advanced CAD tools, people are now able to design multimillion gate chips. Generally, each of these tools has its specific view and model of the world. To represent designs in such a way that tools can understand and manipulate them, one needs to use certain languages. Hardware Description Languages (HDLs) like Verilog or VHDL are developed as description languages or simulator programming languages to describe the behavior of circuits at various abstraction levels. However, they suffer from the fact that they are based on the event-driven model, which does not match well with the Finite State Machine (FSM) model which is used by lots of synthesis, cycle-simulation, or verification engines. Therefore, one needs to maintain multi...

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