In this paper, we propose an efficient algorithm to reduce glitch power dissipation in CMOS logic circuits. The proposed algorithm takes path balancing approach that is achieved by gate sizing and buffer insertion methods. The gate sizing technique reduces not only glitches, but also effective capacitance in the circuit. After gate sizing, buffer insertion is performed for those remaining unbalanced paths that are not covered by gate sizing. Buffers are inserted between the gates where power reduction achieved by glitch reduction is larger than the power consumed by the inserted buffers. The ILP (Integer Linear Program) has been employed to determine the location of inserted buffers, which is a very difficult problem because the power reduction by buffer insertion is closely related to other inserted buffers. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show that 61.5 % of glitch reduction and 30.4 % of power reduction are achieved without increasing the critical path delay.