Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

We propose to use the dominant time constant of a resistor-capacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interesting design problems as convex optimization problems, specifically, semidefinite programs (SDPs). For example, assuming that the conductances and capacitances are affine functions of the design parameters (which is a common model in transistor or interconnect wire sizing), one can minimize the power consumption or the area subject to an upper bound on the dominant time constant, or compute the optimal tradeoff surface between power, dominant time constant, and area. We will also note that, to a certain extent, convex optimization can be used to design the topology of the interconnect wires. This approach has two advantages over methods based on Elmore delay optimization. First, it handles a far wider class of circuits, e.g., those with non-grounded capacitors. Second, it always results in convex optimization problems for which very efficient interiorpoint methods have recently been developed. We illustrate the method, and extensions, with several examples involving optimal wire and transistor sizing.

The problem of sizing gates for power-delay tradeoffs is of great interest to designers. In this work, the theoretical basis for gate sizing under delay and power considerations is presented, and results on a practical implementation are presented. The dynamic power as well as the short-circuit power are modeled, using notions of delay and transition density, and the optimization problem is formulated using notions of convex programming. Previous approaches have not modeled the short circuit power, and our experimental results show that the incorporation of this leads to counter-intuitive results where the minimumpower circuit is not necessarily the minimum-sized circuit.

A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives the primary inputs of the checker are analyzed to order them such that switching activity (and hence power consumption) in the checker is minimized. The reduction in power consumption comes at no additional impact to area or performance and does not require any alteration to the design flow. Since the number of possible input orders increases exponentially in the number of inputs to the checker, the computational costs of determining the optimum order can be very expensive. We present a very effective technique to build a reduced cost function to solve the optimization problem to find a near optimal order.

The problem of power-delay tradeoffs in transistor sizing is examined using a nonlinear optimization formulation. Both the dynamic and the short-circuit power are considered, and a new modeling technique is used to calculate the short-circuit power. The notion of transition density is used, with an enhancement that considers the effect of gate delays on the transition density. When the short-circuit power is neglected, the minimum power circuit is identical to the minimum area circuit. However, under our more realistic models, our experimental results on several circuits show that the minimum power circuit is not necessarily the same as the minimum area circuit.

This paper addresses the optimization of a circuit for low power using transistor reordering. The optimization algorithm relies on a stochastic model of a static CMOS gate that includes the power of internal nodes of the gate. This power-consumption model depends on the switching activity and the equilibrium probabilities of the inputs of the gate. The model allows an exploration of the different configurations of a gate that are obtained by reordering its transistors. Thus, the best configuration of each gate is selected and the overall power consumption of the circuit is reduced. 1 Introduction The continuous increasing packing density and clock frequency of static CMOS circuits has pushed low power as one of the principal design parameters, specially in batterypowered portable systems, such as note-pad computers, personal digital assistants, multi-media terminals and mobile telephones. This paper addresses the optimization of a circuit for low power using transistor reordering fr...

Since busses take up significant fraction of chip-area, the bus capacitances are often considerable, and the bus power may account for as much as 40 % of the total power consumed on the chip [5]. In applications where the integrity of data is not very important, data may bechanged by 3 to 5 % without losing too much information. One such application is that of a binary-encoded image, in which case the human eye cannot perceive the small change. However, these small changes can signi cantly reduce the number of transitions on the data bus and thus the power/energy consumed. We address the following problem: Given a sequence of nk-bit data words and an error-tolerance e % (i.e., at most e % of the data bits are permitted to change), select the bits to be modified so that the total number of transitions is minimized. We show that a greedy strategy is not always optimum. We propose a linear-time dynamic programming based algorithm that generates an optimum solution to this problem. The experimental results for randomly generated data with a uniform distribution indicate that by changing e % data bits, the transitions can be reduced, on average, by 4e%.

Low power design is gaining increasing attention as the market for battery powered portable products expands and as power consumption becomes the stumbling block for further system integration. This paper examines strategies to minimize power consumption of digital circuits by reducing the supply voltage, by using power-conscious design methodologies and tools at the behavioral, logic and circuit levels, and by dynamic power management. The paper highlights some of the more effective and promising approaches for achieving ultra low power VLSI circuits and systems.

This paper presents a survey of layout techniques for designing low power digital CMOS circuits. It describes the many issues facing designers at the physical level of design abstraction and reviews some of the techniques and tools that have been proposed to overcome these difficulties.

The single biggest influence on this work is Nur Touba, who got me started in the field of design automation for VLSI. Nur's unflagging support and encouragement have sustained and driven me throughout the last five years. To the extent that the work presented herein is worthy of credit, Nur deserves a large portion of that credit. His standards in professionalism, integrity, and honesty have raised the bar of excellence for me to follow. Another important influence is Gustavo De Veciana, whose professional life is grounded in a deep understanding of and love for electrical engineering and the teaching and learning process. Words cannot do justice to express all that Gustavo's mentoring has come to mean to me. Thanks also to Margarida Jacome, not just for her support on my dissertation committee, but also for her encouragement and particularly forceful endorsement that has helped me embark on a career in academics. I must also thank Dinos Moundanos and Jawahar Jain for their part in making my stay at and collaborations with the Fujitsu Laboratories of America highly productive. It was there that I took my first tentative steps into the world of research and there that I found the courage and confidence to pursue my own ideas. I would also like to