This paper describes a highly efficient and numerically stable algorithm for the iterative computation of dominant poles and zeros of large linear networks. The algorithm is based on a new implementation of the Pad'e approximation via the Lanczos process. This implementation has considerably superior numerical properties, while maintaining the same computational efficiency as its predecessors. In addition, the algorithm provides a bound on the pole approximation error. 1 Introduction Circuit simulation tasks, such as the accurate prediction of interconnect effects at the board and chip level, or analog circuit analysis with full accounting of parasitic elements, may require the solution of large linear networks. These networks can become extremely large, especially when circuits are automatically extracted from layout, or contain models of distributed elements, such as transmission lines, ground planes, antennas, and other three-dimensional 2 Peter Feldmann and Roland W. Freund stru...

Since the first papers on asymptotic waveform evaluation (AWE), Padé-based reduced-order models have become standard for improving coupled circuit-interconnect simulation efficiency. Such models can be accurately computed using bi-orthogonalization algorithms like Padé via Lanczos (PVL), but the resulting Padé approximates can still be unstable even when generatedfrom stable RLC circuits. For certain classes of RC circuits it has been shown that congruence transforms, like the Arnoldi algorithm, can generate guaranteed stable and passive reduced-order models. In this paper we present a computationally efficient model-order reduction technique, the coordinate-transformed Arnoldi algorithm, and show that this method generates arbitrarily accurate and guaranteed stable reduced-order models for RLC circuits. Examples are presented which demonstrates the enhanced stability and efficiency of the new method.

Reduced-order modeling techniques are now commonly used to efficiently simulate circuits combined with interconnect, but generating reduced-order models from realistic 3-D structures has received less attention. In this paper we describe a Krylov-subspace based method for deriving reduced-order models directly from the 3-D magnetoquasistatic analysis program FastHenry. This new approach is no more expensive than computing an impedance matrix at a single frequency.

In recent years, reduced-order modeling techniques based on Krylov-subspace iterations, especially the Lanczos algorithm and the Arnoldi process, have become popular tools to tackle the large-scale time-invariant linear dynamical systems that arise in the simulation of electronic circuits. This paper reviews the main ideas of reduced-order modeling techniques based on Krylov subspaces and describes the use of reduced-order modeling in circuit simulation. 1 Introduction Krylov-subspace methods, most notably the Lanczos algorithm [81, 82] and the Arnoldi process [5], have long been recognized as powerful tools for large-scale matrix computations. Matrices that occur in large-scale computations usually have some special structures that allow to compute matrix-vector products with such a matrix (or its transpose) much more efficiently than for a dense, unstructured matrix. The most common structure is sparsity, i.e., only few of the matrix entries are nonzero. Computing a matrix-vector pr...

Means of applying Krylov subspace techniques for adaptively extracting accurate reducedorder models of large-scale nonlinear dynamical systems is a relatively open problem. There has been much current interest in developing such techniques. We focus on a bi-linearization method, which extends Krylov subspace techniques for linear systems. In this approach, the nonlinear system is first approximated by a bilinear system through Carleman bilinearization. Then a reduced-order bilinear system is constructed in such a way that it matches certain number of multimoments corresponding to the first few kernels of the Volterra-Wiener representation of the bilinear system. It is shown that the two-sided Krylov subspace technique matches significant more number of multimoments than the corresponding one-side technique.

Decreasing slew rates and efforts to reduce the RC delays of on-chip interconnect through design and technology have resulted in the growing importance of inductance in analyzing interconnect response for timing and noise analysis. In this paper, we consider a practical approach for extracting approximate inductances of on-chip interconnect. This approach, which we call the method of return-limited inductances, is based on performing the inductance modelling of signal lines and power-ground lines independently and on taking advantage of the power and ground distribution of the chip to localize inductive coupling. A set of simple geometry-based matrix decomposition rules guide sparsification in these extractions. Keywords--- inductance, parasitic extraction, signal integrity I. Introduction W ITH technology scaling, chips consist of more interconnect wires of smaller cross sections packed closer together. As a result, RC delays have become an important performance limitation, and cap...

Abstract. Krylov subspace based moment matching algorithms, such as PVL (Padé approximation Via the Lanczos process), have emerged as popular tools for efficient analyses of the impulse response in a large linear circuit. In this work, a new derivation of the PVL algorithm is presented from the matrix point of view. This approach simplifies the mathematical theory and derivation of the algorithm. Moreover, an explicit formulation of the approximation error of the PVL algorithm is given. With this error expression, one may implement the PVL algorithm that adaptively determines the number of Lanczos steps required to satisfy a prescribed error tolerance. A number of implementation issues of the PVL algorithm and its error estimation are also addressed in this paper. A generalization to a multiple-input-multiple-output circuit system via a block Lanczos process is also given.

Extracting the inductance of complex interconnect topologies is a formidable task, and simulating the resulting dense partial inductance matrix is even more difficult. Furthermore, it is well known that simply discarding smallest terms to sparsify the inductance matrix can render the partial inductance matrix indefinite and result in an unstable circuit model. In this paper, we describe a methodology for incrementally generating a sparse partial inductance matrix based on using moments about s=0 to determine when a sufficient number of mutual inductances have been captured. The minimally required mutual inductances are extracted for a provably stable model. 1.0 Introduction Inductance extraction is difficult because mutual inductance depends on the current return path --- which is unknown prior to extracting and simulating a circuit model. Rosa introduced the concept of partial inductances [1][5] to avoid this difficulty by assuming that each segment has a return current at infinity....

This paper presents a set of transformations called "Split Congruence Transformations" (SCT's) which can be used to accurately reduce a RLC network while preserving passivity.

. We describe the application of the PVL algorithm to the small-signal analysis of circuits, including sensitivity computations. The PVL algorithm is based on the efficient computation of the Pad'e approximation of the network transfer function via the Lanczos process. The numerical stability of the algorithm permits the computation of the Pad'e approximation to any accuracy over a certain frequency range. We extend the algorithm to compute sensitivities of network transfer functions, their poles, and their zeros, with respect to arbitrary circuit parameters, with minimal additional computational cost. We demonstrate the implementation of our algorithm on circuit examples. 1 Introduction The process of analyzing analog circuits with full accounting of parasitic elements, interconnect analysis at the board or chip level, and numerous other circuit-simulation tasks often require the analysis of large linear networks. These networks can become extremely large, especially when circuits ar...