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85
Efficient linear circuit analysis by Padé approximation via the Lanczos process
, 1994
"... This paper describes a highly efficient and numerically stable algorithm for the iterative computation of dominant poles and zeros of large linear networks. The algorithm is based on a new implementation of the Pad'e approximation via the Lanczos process. This implementation has considerably superio ..."
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Cited by 219 (31 self)
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This paper describes a highly efficient and numerically stable algorithm for the iterative computation of dominant poles and zeros of large linear networks. The algorithm is based on a new implementation of the Pad'e approximation via the Lanczos process. This implementation has considerably superior numerical properties, while maintaining the same computational efficiency as its predecessors. In addition, the algorithm provides a bound on the pole approximation error. 1 Introduction Circuit simulation tasks, such as the accurate prediction of interconnect effects at the board and chip level, or analog circuit analysis with full accounting of parasitic elements, may require the solution of large linear networks. These networks can become extremely large, especially when circuits are automatically extracted from layout, or contain models of distributed elements, such as transmission lines, ground planes, antennas, and other threedimensional 2 Peter Feldmann and Roland W. Freund stru...
A CoordinateTransformed Arnoldi Algorithm for Generating Guaranteed Stable ReducedOrder Models of RLC Circuits
, 1996
"... Since the first papers on asymptotic waveform evaluation (AWE), Padébased reducedorder models have become standard for improving coupled circuitinterconnect simulation efficiency. Such models can be accurately computed using biorthogonalization algorithms like Padé via Lanczos (PVL), but the res ..."
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Cited by 65 (14 self)
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Since the first papers on asymptotic waveform evaluation (AWE), Padébased reducedorder models have become standard for improving coupled circuitinterconnect simulation efficiency. Such models can be accurately computed using biorthogonalization algorithms like Padé via Lanczos (PVL), but the resulting Padé approximates can still be unstable even when generatedfrom stable RLC circuits. For certain classes of RC circuits it has been shown that congruence transforms, like the Arnoldi algorithm, can generate guaranteed stable and passive reducedorder models. In this paper we present a computationally efficient modelorder reduction technique, the coordinatetransformed Arnoldi algorithm, and show that this method generates arbitrarily accurate and guaranteed stable reducedorder models for RLC circuits. Examples are presented which demonstrates the enhanced stability and efficiency of the new method.
ReducedOrder Modeling Techniques Based on Krylov Subspaces and Their Use in Circuit Simulation
 Applied and Computational Control, Signals, and Circuits
, 1998
"... In recent years, reducedorder modeling techniques based on Krylovsubspace iterations, especially the Lanczos algorithm and the Arnoldi process, have become popular tools to tackle the largescale timeinvariant linear dynamical systems that arise in the simulation of electronic circuits. This pape ..."
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Cited by 53 (10 self)
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In recent years, reducedorder modeling techniques based on Krylovsubspace iterations, especially the Lanczos algorithm and the Arnoldi process, have become popular tools to tackle the largescale timeinvariant linear dynamical systems that arise in the simulation of electronic circuits. This paper reviews the main ideas of reducedorder modeling techniques based on Krylov subspaces and describes the use of reducedorder modeling in circuit simulation. 1 Introduction Krylovsubspace methods, most notably the Lanczos algorithm [81, 82] and the Arnoldi process [5], have long been recognized as powerful tools for largescale matrix computations. Matrices that occur in largescale computations usually have some special structures that allow to compute matrixvector products with such a matrix (or its transpose) much more efficiently than for a dense, unstructured matrix. The most common structure is sparsity, i.e., only few of the matrix entries are nonzero. Computing a matrixvector pr...
Efficient ReducedOrder Modeling of FrequencyDependent Coupling Inductances associated with 3D Interconnect Structures
, 1994
"... Reducedorder modeling techniques are now commonly used to efficiently simulate circuits combined with interconnect, but generating reducedorder models from realistic 3D structures has received less attention. In this paper we describe a Krylovsubspace based method for deriving reducedorder mode ..."
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Cited by 52 (10 self)
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Reducedorder modeling techniques are now commonly used to efficiently simulate circuits combined with interconnect, but generating reducedorder models from realistic 3D structures has received less attention. In this paper we describe a Krylovsubspace based method for deriving reducedorder models directly from the 3D magnetoquasistatic analysis program FastHenry. This new approach is no more expensive than computing an impedance matrix at a single frequency.
Krylov Subspace Techniques for ReducedOrder Modeling of Nonlinear Dynamical Systems
 Appl. Numer. Math
, 2002
"... Means of applying Krylov subspace techniques for adaptively extracting accurate reducedorder models of largescale nonlinear dynamical systems is a relatively open problem. There has been much current interest in developing such techniques. We focus on a bilinearization method, which extends Kry ..."
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Cited by 50 (3 self)
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Means of applying Krylov subspace techniques for adaptively extracting accurate reducedorder models of largescale nonlinear dynamical systems is a relatively open problem. There has been much current interest in developing such techniques. We focus on a bilinearization method, which extends Krylov subspace techniques for linear systems. In this approach, the nonlinear system is first approximated by a bilinear system through Carleman bilinearization. Then a reducedorder bilinear system is constructed in such a way that it matches certain number of multimoments corresponding to the first few kernels of the VolterraWiener representation of the bilinear system. It is shown that the twosided Krylov subspace technique matches significant more number of multimoments than the corresponding oneside technique.
Error estimation of the Pad'e approximation of transfer functions via the Lanczos process
 Trans. Numer. Anal
, 1998
"... Abstract. Krylov subspace based moment matching algorithms, such as PVL (Padé approximation Via the Lanczos process), have emerged as popular tools for efficient analyses of the impulse response in a large linear circuit. In this work, a new derivation of the PVL algorithm is presented from the matr ..."
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Cited by 25 (8 self)
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Abstract. Krylov subspace based moment matching algorithms, such as PVL (Padé approximation Via the Lanczos process), have emerged as popular tools for efficient analyses of the impulse response in a large linear circuit. In this work, a new derivation of the PVL algorithm is presented from the matrix point of view. This approach simplifies the mathematical theory and derivation of the algorithm. Moreover, an explicit formulation of the approximation error of the PVL algorithm is given. With this error expression, one may implement the PVL algorithm that adaptively determines the number of Lanczos steps required to satisfy a prescribed error tolerance. A number of implementation issues of the PVL algorithm and its error estimation are also addressed in this paper. A generalization to a multipleinputmultipleoutput circuit system via a block Lanczos process is also given.
ReturnLimited Inductances: A Practical Approach to OnChip Inductance Extraction
, 1999
"... Decreasing slew rates and efforts to reduce the RC delays of onchip interconnect through design and technology have resulted in the growing importance of inductance in analyzing interconnect response for timing and noise analysis. In this paper, we consider a practical approach for extracting appro ..."
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Cited by 24 (3 self)
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Decreasing slew rates and efforts to reduce the RC delays of onchip interconnect through design and technology have resulted in the growing importance of inductance in analyzing interconnect response for timing and noise analysis. In this paper, we consider a practical approach for extracting approximate inductances of onchip interconnect. This approach, which we call the method of returnlimited inductances, is based on performing the inductance modelling of signal lines and powerground lines independently and on taking advantage of the power and ground distribution of the chip to localize inductive coupling. A set of simple geometrybased matrix decomposition rules guide sparsification in these extractions. Keywords inductance, parasitic extraction, signal integrity I. Introduction W ITH technology scaling, chips consist of more interconnect wires of smaller cross sections packed closer together. As a result, RC delays have become an important performance limitation, and cap...
grid physics and implications for CAD
 in Proc. DAC
, 2006
"... Much research has been done lately concerning analysis and optimization techniques for onchip power grid networks. However, all of these approaches assume a particular model or behavior of the power delivery. In this paper, we describe the first detailed fulldie dynamic model of an industrial micr ..."
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Cited by 19 (1 self)
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Much research has been done lately concerning analysis and optimization techniques for onchip power grid networks. However, all of these approaches assume a particular model or behavior of the power delivery. In this paper, we describe the first detailed fulldie dynamic model of an industrial microprocessor design, including package and nonuniform decap distribution. This model is justified from the ground up using a fullwave model and then increasingly larger but less detailed models with only the irrelevant elements removed. Using these models we show that there is little impact of ondie inductance in such a design, and that the package is critical to understanding resonant properties of the grid. We also show that transient effects are sensitive to nonuniform decap distribution and that locality is a tight function of frequency and of the packagedie resonance, producing newly explained localized resonant effects. Specifically, all of these points have impact on what kind of analysis and optimization are required from CAD. Categories & Subject Descriptors:
Preservation of Passivity During RLC Network Reduction via Split Congruence Transformations
, 1997
"... This paper presents a set of transformations called "Split Congruence Transformations" (SCT's) which can be used to accurately reduce a RLC network while preserving passivity. ..."
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Cited by 18 (0 self)
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This paper presents a set of transformations called "Split Congruence Transformations" (SCT's) which can be used to accurately reduce a RLC network while preserving passivity.
Formulae and Applications of Interconnect Estimation Considering Shield Insertion and Net Ordering
, 2001
"... It has been shown recently that simultaneous shield insertion and net ordering (called SINO/R as only random shields are used) provides an areaefficient solution to reduce the RLC noise. In this paper, we first develop simple formulae with errors less than 10% to estimate the number of shields in t ..."
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Cited by 17 (1 self)
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It has been shown recently that simultaneous shield insertion and net ordering (called SINO/R as only random shields are used) provides an areaefficient solution to reduce the RLC noise. In this paper, we first develop simple formulae with errors less than 10% to estimate the number of shields in the minarea SINO/R solution. In order to accommodate prerouted P/G wires that also serve as shields, we then formulate two new SINO problems: SINO/SPR and SINO/UPG, and propose effective and efficient twophase algorithms to solve them. Compared to the existing dense wiring fabric scheme, the resulting SINO/SPR and SINO/UPG schemes maintain the regularity of the P/G structure, have negligible penalty on noise and delay variation, and reduce the total routing area by up to 42% and 36%, respectively. Various estimation results developed in this paper can be readily used to guide global routing and highlevel design decisions.