Wide issue superscalar and VLIW processors utilize instruction-level parallelism (ILP) to achieve high performance. However, if insufficient ILP is found, the performance potential of these processors suffers dramatically. Branch instructions, which are one of the major limitations to exploiting ILP, enforce strict ordering conditions in programs to ensure correct execution. Therefore, it is difficult to achieve the desired overlap of instruction execution with branches in the instruction stream. To effectively exploit ILP in the presence of branches requires efficient handling of branches and the dependences they impose. This dissertation investigates two techniques for exposing and enhancing ILP in the presence of branches, speculative execution and predicated execution. Speculative execution enables an ILP compiler to remove dependences between instructions and prior branches. In this manner, the execution of instructions and predicted future instructions may be overlapped. Compiler-controlled speculative execution is employed using an efficient structure called the superblock. The formation and optimization of superblocks increase ILP along important execution paths by systematically removing constraints due to unimportant paths. In conjunction with superblock optimizations, speculative execution is utilized to remove control dependences in the superblock

... to support low-level optimization and scheduling. A dynamic approach, the memory conflict buffer, originally proposed by Chen [1], is analyzed across a large suite of integer and floating-point benchmarks. A new static approach, termed sync arcs, involving the passing of explicit dependence arcs from the source-level code down to the low-level code, is proposed and evaluated. This investigation of both dynamic and static memory disambiguation allows a quantitative analysis of the tradeoffs between the two approaches.

... over other software pipelining techniques based on global scheduling. The ICTs are applied to Modulo Scheduling to schedule loops with conditional branches. Experimental results show that this approach allows more flexible scheduling and thus better performance than Modulo Scheduling with Hierarchical Reduction. Modulo Scheduling with ICTs targets processors with no or limited support for conditional execution such as superscalar processors. However, in processors that do not require instruction set compatibility, support for Predicated Execution can be used. This dissertation shows that Modulo Scheduling with Predicated Execution has better performance and lower code expansion than Modulo Scheduling with ICTs on processors without special hardware support.

... depends on speculative support to achieve high performance [5]. Without speculative support, very little execution overlap between loop iterations is achieved. This dissertation discusses the problems that must be addressed to perform compile-time speculation for acyclic global scheduling, classi es existing speculation models based upon how they solve these problems and discusses two new compile-time or compiler-controlled speculation models- write-back suppression speculation and safe speculation.

Compiler-controlled speculative execution has been shown to be e ective in increasing the available instruction level parallelism (ILP) found in non-numeric programs. An important problem with compiler-controlled speculative execution is to accurately report and handle exceptions caused by speculatively executed instructions. Previous solutions to this problem incur either excessive hardware overhead or extra register pressure. This paper introduces a new architecture scheme referred to as write-back suppression. This scheme systematically suppresses register le updates for subsequent speculative instructions after an exception condition is detected for a speculatively executed instruction. We show that with a modest amount of hardware, writeback suppression supports accurate reporting and handling of exceptions for compiler-controlled speculative execution without adding to the register pressure. Experiments based on a prototype compiler implementation and hardware simulation indicate that ensuring accurate handling of exceptions with write-back suppression incurs very little run-time performance overhead. Index terms- exception detection, exception recovery, scheduling, speculative execution, VLIW, superscalar 1 1

ion, thanks to Bob Rau, Mike Shlansker and Vinod Kathail of Hewlett-Packard Laboratories for their valuable insights regarding data dependence analysis and code optimization. Thanks to the Fannie and John Hertz Foundation, which awarded me a Graduate Fellowship, providing generous financial support for my graduate studies. Finally, I would like to thank my spouse Matthew, my brothers Greg, Galen, and Gavin, Matt's sister Jennifer and brother in-law Michael, my parents, Paul and Kathy, and Matt's parents Paul and Joann, for their love and support during my graduate studies. v DEDICATION To my spouse Matthew Hesson-McInnis for your love, friendship and support. vi TABLE OF CONTENTS Page 1. INTRODUCTION : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 1 2. DATA DEPENDENCE ANALYSIS BACKGROUND : : : : : : : : : : : : 3 2.1 Data Dependence Analysis Concept : : : : : : : : : : : : : : : : : : : 3 2.2 Value-Based

wininv;L-WLv machin operation to executein parallel. Explicitly Parallel Instruction computing (EPIC) processors evolvedin an attempt to achieve high levels of ILP without signvTn t hardware complexity. To take advan tage of higher level of ILP in EPIC, the ILP compiler must use aggressive a n expen ive optimization techn# ues leadin to in#T-ZvV compilation time. If the size a n shape of thecompilation unm is limited, thecompilation time can be reduced. But this limited scope of compilation may restrict the scope of the optimization thuslimitin theamoun t of performanV improvemen t that can be achieved. As a result, the compiler may gen;x te lesse#cien t code. Region - based compilation has been proposed asan approach for copin with this problem, nx ely con tainZF compilation cost without compromisin execution performa n e. In regionTF; ed compilation execution frequen ies are used to guide compiler optimization , with moreatten tion given to the region of the program

This paper shows that static profiling is effective yet not as effective as dynamic profiling. Hyperblock formation has some interesting differences to superblock formation that could make it an 61

It is increasingly necessary for the compiler to overlap successive loop iterations in order to nd su cient instruction-level parallelism to e ectively utilize the resources of high-performance processors. Two competing methods have been developed for moving instructions across itera-tion boundaries: unrolling followed by global acyclic scheduling and software pipelining. This dissertation investigates modulo scheduling, a software pipelining technique. Much of the pre-vious work on modulo scheduling has targeted the relatively well-behaved loops in numeric programs. This dissertation develops new techniques that allow modulo scheduling to be ef-fectively applied to control-intensive non-numeric programs. These techniques overcome the restrictions imposed by problematic control ow and loop exits. This dissertation also demonstrates that unrolling-based optimization prior to scheduling improves the performance of modulo scheduled loops and is, in fact, necessary to allow modulo scheduling to surpass the performance of acyclic scheduling for control-intensive general-purpose programs. Modulo scheduling has the following advantages over the acyclic scheduling approach for control-intensive general-purpose programs. First, modulo scheduling increases performance by maintaining the overlap of loop iterations throughout the execution of the loop. Second,

This report examines how the compiler can more efficiently use a large number of processor registers. The placement of data items into registers, called register allocation, is known to be one of the most important compiler optimizations for high-speed computers because registers are the fastest storage devices in the computer system. However, register allocation has been limited in scope because of aliasing in the memory system. To break this limitation and allow more data to be placed into registers, new compiler and microarchitecture support is needed. We propose the modification of register access semantics to include an indirect access mode. We call this optimization the Smart Register File. The smart register file allows the relaxation of overly-conservative assumptions in the compiler by having the hardware provide support for aliased data items in processor registers. As a result, the compiler can allocate data from a larger pool of candidates than in a conventional system. An...