Symbolic analog-circuit analysis has many applications, and is especially useful for analog synthesis and testability analysis. Existing approaches rely on two forms of symbolic expression representation: expanded sum-of-product form or arbitrarily nested form. Expanded form suffers the problem that the number of product terms grows exponentially with the size of a circuit, and approximation has to be used. Nested form is not canonical, i.e., many representations exist for a symbolic expression, and manipulations with the nested form are often complicated. In this paper, we present a new approach to exact and canonical symbolic analysis by exploiting the sparsity and sharing of product terms. It consists of representing the symbolic determinant of a circuit matrix by a graph---called determinant decision diagram (DDD)---and performing symbolic analysis by graph manipulations. We showed that DDD construction, as well as many symbolic analysis algorithms, can be performed in time complex...

A novel algorithm is presented that generates approximate symbolic expressions for small-signal characteristics of large analog integrated circuits. The method is based upon the approximation of an expression while it is being computed. The CPU time and memory requirements are reduced drastically with regard to previous approaches, as only those terms are calculated which will remain in the final expression. As a consequence, the maximum circuit size amenable to symbolic analysis has largely increased. The simplification procedure explicitly takes into account variation ranges of the symbolic parameters to avoid inaccuracies of conventional approaches which use a single value. The new approach is also able to take into account mismatches between the symbolic parameters. INTRODUCTION Symbolic circuit analysis refers to the calculation of network functions H(s,x) in the form: (1) where x T ={x 1 , x 2 , . . . x Q } is the vector of circuit parameters which remain as symbols, and the...

In recent years, the technique of simpl$cation during gen-eration has turned out to be very promising for the eficient computation of approximate symbolic network functions for large transistor circuits. In this paper it is shown how sym-bolic network functions can be simpl$ed during their genera-tion with any well-known symbolic network analysis method. The underlying algorithm for the different techniques is al-ways a matroid intersection algorithm. It is shown that the most eflcient technique is the two-graph method. An imple-mentation of the simpltjication during generation technique with the two-graph method illustrates its benefits for the sym-bolic analysis of large analog circuits. 1

Abstract — Efficient algorithms are presented to generate approximate expressions for transfer functions and characteristics of large linear analog circuits. The algorithms are based on a compact determinant decision diagram (DDD) representation of exact transfer functions and characteristics. Several theoretical properties of DDDs are characterized, and three algorithms, namely, based on dynamic programming, based on consecutive k-shortest path based, and based on incremental k-shortest path, are presented in this paper. We show theoretically that all three algorithms have time complexity linearly proportional to |DDD|, the number of vertices of a DDD, and that the incremental kshortest path based algorithm is fastest and the most flexible one. Experimental results confirm that the proposed algorithms are the most efficient ones reported so far, and are capable of generating thousands of dominant terms for typical analog blocks in CPU seconds on a modern computer workstation. Index Terms — analog symbolic analysis, circuit simulation, determinant decision diagrams, matrix determinant, behavioral modeling I.

This paper addresses the problems arising in the calculation of numerical references (network function coefficients) , essential for an appropriate error control in simplification before and during generation algorithms for symbolic analysis of large analog circuits. The conventional polynomial interpolation method reveals to be unable to handle the large circuit sizes needed, mainly due to the dramatic effect of round-off errors. This paper introduces a new algorithm able to accurately calculate the network function coefficients of large analog circuits in an efficient way. 1. Introduction Symbolic circuit analysis refers to the calculation of network functions where all or part of the circuit parameters are represented by symbols. The applicability of symbolic simulation techniques to the analysis and synthesis of analog integrated circuits has been known for a long time. See for instance [1] for an actualized review of techniques and applications of symbolic analysis. Given the e...

This paper reviews the main last generation symbolic analyzers, comparing them in terms of functionality, pointing out also their shortcomings. The state-of-the-art in this field is also studied, pointing out directions for future research. 1. INTRODUCTION Circuit analysis is a basic milestone for efficient design of integrated circuits. Ever since powerful computers have been available, designers have developed programs to analyze circuits automatically. Today, all electrical engineering professionals and students use electrical simulators (such as HSPICE or ELDO). However, electrical simulators do not cover all the analysis tasks required for integrated circuit design. Essentially, they only serve to verify the performance of previously sized circuits. Among other things, designers must be able to predict the behavior of unsized circuits by tracing relationships among performance figures and design parameters. These relationships may be in the form of transfer functions, poles and ...

An interface to symbolic circuit analysis has been developed for a SPICE--like circuit simulator in order to integrate numerical simulation with an existing program for symbolic circuit analysis. In effect, both numerical and symbolic analyses use the same internal representation of circuits which makes the two approaches truly complementary. This integrated simulation capability is used in simulation--based parameter extraction where all ac small-signal parameters are fitted through the symbolic analysis rather than numerical one, significantly reducing the execution time of the extraction process. INTRODUCTION Increasing demand for electronic components results in rapidly growing both the scale and the size of electronic circuits. This continuously creates needs for new and more efficient analog methods for circuit analysis. Integration of numerical and symbolic circuit analyses is one of possible improvements than can be used to increase the efficiency of circuit analysis tools. ...

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In its original form, the two-graph method allows only circuit components that are described by a v-i relationship of the admittance type (G, C, g m). In particular, it excludes resistors (expressed as resistance R rather ten conductance G), inductors and current-controlled current sources. Practising circuit designers often prefer to have symbolic analysis results expressed in terms of resistances, current or voltage gains, or other symbols that cannot be represented by admittances. This paper describes a simple modification of the two-graph method that allow symbolic analysis of circuits containing components other than admittances. The twograph method is extended by introducing new element stamps for all non-admittance components.

In this paper, we present a technique for estimating the gain, bandwidth, power and area of analog integrated circuits. A two-step approach is adopted to speed up the estimation process and handle larger analog systems. In the first step, the performance of basic analog components is estimated using a knowledge-based approach. Then, component models are generated with the estimates produced at this phase. In the second phase, we use a symbolic analysis methodology to evaluate the performance at the system level. The system net-list is represented by a signal flow graph (SFG) using the component models generated at the previous phase. The SFG approach allows to handle feedback loops at the system level. 1 Introduction The analog synthesis process consists of two phases: topology selection and circuit sizing [1]. During the topology selection process, a net-list of components selected from a pre-defined library is generated. The generated topology should meet the specification requirem...