A new technique for generating approximate symbolic expressions for network functions in linear(ized) analog circuits is presented. It is based on the compact determinant decision diagram (DDD) representation of the circuit. An implementation of a term generation algorithm is given and its performance is compared to a matroidbased algorithm. Experimental results indicate that our approach is the fastest reported algorithm so far for this application.

This paper introduces a new hierarchical analysis methodology which incorporates approximation strategies during the analysis process. Consequently, the circuit sizes that can be analyzed increase dramatically, without suffering from the combinatorial explosion of expression complexity. Moreover, the interpretability and usability in practical applications is enabled by providing analytical models that keep complexity at a minimum with the prescribed accuracy.

... Tree and forest enumeration expressions for electrical resistance are generalized. We also demonstrate how the corank-nullity polynomial, basis expansions with activities, and a geometric lattice expansion generalize to ported Tutte functions of oriented matroids. The ported Tutte functions are parametrized, which raises the problem of how to generalize known characterizations of parameterized non-ported Tutte functions.

The Tutte equations are ported (or set-pointed) when the equations F(N) = geF(N/e) + reF(N \ e) are omitted for elements e in a distinguished set called ports. The solutions F, called ported Tutte functions, can distinguish different orientations of the same matroid. A ported extensor with ground set is a (fully) decomposable element in the exterior algebra (of antisymmetric tensors) over a vector space with a given basis, called the ground set, containing a distinguished subset called ports. A ported extensor is one way to present a linearly representable ported matroid or oriented matroid. There are extensor operations corresponding to oriented matroid dualization, and to deletions and contractions. We define a ported extensor function by means of dualization, port element renaming, exterior multiplication, and then contraction of all non-port elements. The main result is that this function satisfies a sign-corrected variant of the Tutte equations in which deletion and contraction are extensor operations, and addition and the anticommutative multiplication belong to an exterior algebra rather than

Abstract — A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed graph reduction process and a recursive sign determination algorithm. A symbolic analog circuit simulator is developed using a combination of these techniques. The simulator is able to analyze large analog circuits in the frequency domain. Experimental results are reported. I.