Abstract-- As the CMOS technology enters the very deep submicron era, inter-wire coupling capacitance becomes the dominant part of load capacitance. The coupling effects have brought new challenges to routing algorithms on both delay estimation and optimization. In this paper, we propose a timing-driven global routing algorithm with consideration of coupling effects. The two-phase algorithm based on timing-relax method includes a heuristic Steiner tree algorithm and an optimization algorithm. Experimental results are given to demonstrate the efficiency and accuracy of the algorithm. I.

In deep submicron digital circuits capacitive couplings make delay of a switching signal highly dependent on its neighbors ’ switching times and switching directions. A long path may have a large number of coupling neighbors with difficult to determine interdependencies. Ignoring the mutual relationship among the signals may result in a very pessimistic estimation of circuit delay. In this paper, we apply efficient functional correlation analysis techniques to identify critical paths caused by crosstalk delay effects. We also discuss applications to static timing optimization. Experiments demonstrate efficacy of the proposed technique. 1.

In this paper, we propose a timing dependent dynamic power estimation framework that considers the impact of coupling and glitches. We show that relative switching activities and times of coupled nets significantly affect dynamic power consumption, and neither should be ignored during power estimation. To capture the timing dependence, an approach to efficient representation and propagation of switching-window distributions through a circuit, considering coupling induced delay variations, is developed. Based on the propagated switchingwindow distributions, power consumption in charging or discharging coupling capacitances is calculated, and accounted for in the total power. Experimental results for the ISCAS’85 benchmarks demonstrate that ignoring the impact of timing dependent coupling on power can cause up to 59 % error in coupling power estimation (up to 25 % error in total power estimation). 1

Latches are extensively used in high-performance sequential circuit designs to achieve high frequencies because of their good performance and time borrowing feature. However, the amount of timing uncertainty due to crosstalk accumulated through latches could be larger than the benefit gained by time borrowing. In this paper, we show that the trade-off between a latch and a flop can be leveraged in a sequential circuit design with crosstalk, so that the clock period is minimized by selecting a configuration of mixed latches and flops. A circular time representation is proposed to make coupling detection easier and more efficient. Experiments on our heuristic algorithm for finding an optimal configuration of mixed latches and flops showed promising results.

Abstract- With the exponential reduction in scaling of feature size, inter-wire coupling capacitance becomes the dominant part of load capacitance. Two problems are introduced by coupling, delay deterioration and crosstalk. This paper presents a timing-driven global routing algorithm with consideration of coupling effects and crosstalk avoidance. Our work differs from the existing ones in that we design a global routing “framework” which performs well in routablity, timing, and also facilitate the detailed routing in crosstalk avoidance. Experimental results on industrial circuits show that, the algorithm leads to substantial delay reduction and effective crosstalk elimination. I.

Abstract — This paper presents a framework for fast and accurate static timing analysis considering coupling. With technology scaling to smaller dimensions, the impact of coupling induced delay variations can no longer be ignored. Timing analysis considering coupling is iterative, and can have considerably larger run-times than a single pass approach. We propose a novel and accurate coupling delay model, and present techniques to increase the convergence rate of timing analysis when complex coupling models are employed. Experimental results obtained for the ISCAS benchmarks show promising accuracy improvements using our coupling model while an efficient iteration scheme shows significant speedup (up to 62.1%) in comparison to traditional approaches. I.

This paper addresses verifying the timing of circuits containing level-sensitive latches in the presence of cross talk. We show that three consecutive periodic occurrences of the aggressor's input switching window must be compared with the victim's input switching window. We propose a new phase shift operator to allow aligning the aggressor's three relevant switching windows with the victim's input signals. We solve the problem iteratively in polynomial time, and show an upper bound on the number of iterations equal to the number of capacitors in the circuit. Our experiments demonstrate that eliminating false coupling results in finding a smaller clock period at which a circuit will run.

Abstract — High performance circuits are facing increasingly severe signal integrity problems due to crosstalk noise and crosstalk noise awareness has become an integral part of static timing analysis (STA). Existing crosstalk noise aware STA methods compute noise induced delay uncertainty on a net by net basis and in a pessimistic way, without considering the overlap bounds of the victim and aggressor timing windows and realistic delay impact on early and late signal arrival times. Since crosstalk induced delay on indivudial nets contribute cumulatively on data and clock paths, even small amounts of pessimism in computation can add up to produce several unrealistic timing violations. Unlike glitch noise analysis where noise often attenuates during propagation, quality of delay noise analysis is severely affected by any pessimism in noise estimation and can unnecessarily cost valuable silicon and design resources for fixing unreal violations. In this paper, we propose two temporal techniques to reduce pessimism in crosstalk noise aware STA. The first method, “effective delay noise”, is a net based method where the exact overlap points of victim and aggressor timing windows are considered to obtain the part of delay noise that actually impacts early and late signal arrival times. The second method, “path based delay noise”, is a path based method where the reduced arrival uncertainty of the nets of a given path are utilized for pessimism reduction. We also propose a novel “uncertainty propagation ” technique as part of the second method, which results in an iteration free crosstalk noise aware STA of the path with significantly reduced pessimism. The two techniques are combined in a proposed methodology that is compatible with existing industrial static timing analyzers with very little computational overhead compared to the traditional noise aware STA and a significant improvement in eliminating unreal violations. The proposed techniques resulted in 77% reduction of worst case negative slack and 57 % reduction in the number of failing paths in the setup analysis of a 90nm industrial design. I.

We present, in this paper, novel algorithms to compute the set of “top-k ” aggressors in a design. We show that the computation of the set of top-k aggressors is non-trivial, since we must consider all permutations of aggressors that are coupled to a critical path. Also, different sets of aggressors contribute different amounts of noise to each critical path and a brute-force enumeration to obtain the set of top-k aggressors has impractical runtime. Our proposed approach uses two key techniques to reduce the runtime complexity: Firstly, we model the delay noise propagated from a victim net to its fanout net by a so-called pseudo aggressor, which simplifies our problem formulation significantly. Secondly, we define a dominance property for aggressor sets, which imposes a partial ordering on the aggressor sets and allows us to efficiently prune the enumeration space. We then demonstrate the effectiveness of our proposed algorithm on benchmark circuits.

Abstract—As technology scales to smaller dimensions, increasing process variations and coupling induced delay variations make timing verification extremely challenging. In this paper, the authors establish a theoretical framework for statistical timing analysis with coupling. They prove the convergence of their proposed iterative approach and discuss implementation issues under the assumption of a Gaussian distribution for the parameters of variation. A statistical timer based on their proposed approach is developed and experimental results are presented for the International Symposium on Circuits and Systems benchmarks. They juxtapose their timer with a single pass, noniterative statistical timer that does not consider the mutual dependence of coupling with timing, and another statistical timer that handles coupling deterministically. Monte Carlo simulations reveal a distinct gain (up to 24%) in accuracy by their approach in comparison to the others mentioned. Index Terms—Coupling, fixpoint computation, statistical timing analysis, variability, very large scale integration (VLSI). I.