Ordered Binary-Decision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as graph algorithms on OBDD

. The satisfiability (SAT) problem is a core problem in mathematical logic and computing theory. In practice, SAT is fundamental in solving many problems in automated reasoning, computer-aided design, computeraided manufacturing, machine vision, database, robotics, integrated circuit design, computer architecture design, and computer network design. Traditional methods treat SAT as a discrete, constrained decision problem. In recent years, many optimization methods, parallel algorithms, and practical techniques have been developed for solving SAT. In this survey, we present a general framework (an algorithm space) that integrates existing SAT algorithms into a unified perspective. We describe sequential and parallel SAT algorithms including variable splitting, resolution, local search, global optimization, mathematical programming, and practical SAT algorithms. We give performance evaluation of some existing SAT algorithms. Finally, we provide a set of practical applications of the sat...

Ordered Binary Decision Diagrams (OBDDs) have found widespread use in CAD applications such as formal verification, logic synthesis, and test generation. OBDDs represent Boolean functions in a form that is both canonical and compact for many practical cases. They can be generated and manipulated by efficient graph algorithms. Researchers have found that many tasks can be expressed as series of operations on Boolean functions, making them candidates for OBDD-based methods. The success of OBDDs has inspired efforts to improve their efficiency and to expand their range of applicability. Techniques have been discovered to make the representation more compact and to represent other classes of functions. This has led to improved performance on existing OBDD applications, as well as enabled new classes of problems to be solved. This paper provides an overview of the state of the art in graph-based function representations. We focus on several recent advances of particular importance for forma...

OBDD's are the state-of-the-art data structure for Boolean function manipulation since basic tasks of Boolean manipulation such as testing equivalence, satisfiability, or tautology, and performing single Boolean synthesis steps can be done efficiently. In the following we show that the efficient manipulation of OBDD's can be extended to a more general data structure, so-called FBDD's. In detail, the advantages of using FBDD's instead of OBDD's are ffl FBDD's are generally more (sometimes even exponentially more) succinct than OBDD's, ffl FBDD's provide, similarly to OBDD's, canonical representations of Boolean functions, and ffl in terms of FBDD's basic tasks of Boolean manipulation can be performed similarly efficient as in terms of OBDD's. The power of the FBDD-concept is demonstrated by showing that the verification of the benchmark circuit design for the hidden weighted bit function HWB proposed by Bryant can be carried out efficiently in terms of FBDD's while, for princip...

. We prove that read-once branching programs computing integer multiplication require size 2 ## # n) . This is the first nontrivial lower bound for multiplication on branching programs that are not oblivious. By the appropriate problem reductions, we obtain the same lower bound for other arithmetic functions. Key words. multiplication, read-once, branching programs, BDD, verification AMS subject classifications. 68Q05, 68Q25, 68M15 PII. S0097539795290349 1. Introduction and background. It is well known that many functions, some of them very simple, cannot be computed by read-once branching programs of polynomial size [We88, Za84, Du85, We87, BHST87, Ju88, Kr88]. Interest in whether integer multiplication can be so computed has been created by recent developments in the field of digital design and hardware verification. 1.1. Hardware verification and branching programs. The central problem of verification is to check whether a combinational hardware circuit has been correctly designe...

The satisfiability (SAT) problem is a fundamental problem in mathematical logic, inference, automated reasoning, VLSI engineering, and computing theory. In this paper, following CNF and DNF local search methods, we introduce the Universal SAT problem model, UniSAT, that transforms the discrete SAT problem on Boolean space f0; 1g m into an unconstrained global optimization problem on real space E m . A direct correspondence between the solution of the SAT problem and the global minimum point of the UniSAT objective function is established. Many existing global optimization algorithms can be used to solve the UniSAT problems. Combined with backtracking /resolution procedures, a global optimization algorithm is able to verify satisfiability as well as unsatisfiability. This approach achieves significant performance improvements for certain classes of conjunctive normal form (CNF ) formulas. It offers a complementary approach to the existing SAT algorithms.

. A major challenge in the area of hardware verification is to devise methods that can handle circuits of practical size. This paper intends to show how the applicability of combinational circuit verification tools based on binary decision diagrams (BDDs) can be greatly improved. The introduction of dynamic variable ordering techniques already makes these tools more robust; a designer no longer needs to worry about a good initial variable order. In addition, we present a novel approach combining BDDs with a technique that exploits structural similarities of the circuits under comparison. We explain how these similarities can be detected and put to effective use in the verification process. Benchmark results show that the proposed method significantly extends the range of circuits that can be verified using BDDs. 1 Introduction The times when researchers in the CAD field could sit in their ivory tower thinking up neat solutions for theoretical problems belong to the past. Nowadays, ind...

Pass Transistor Logic has attracted more and more interest during last years, since it has proved to be an attractive alternative to static CMOS designs with respect to area, performance and power consumption. Existing automatic PTL synthesis tools use a direct mapping of (decomposed) BDDs to pass transistors. Thereby, structural properties of BDDs like the ordering restriction and the fact that the select signals of the multiplexers (corresponding to BDD nodes) directly depend on input variables, are imposed on PTL circuits although they are not necessary for PTL synthesis.

Binary Decision Diagrams have been widely used to solve the Boolean Satisfiability (SAT) problem. The individual constraints can be represented using BDDs and the conjunction of all constraints provides all satisfying solutions. However, BDD-related SAT techniques suffer from size explosion problems. This paper presents two BDD-based algorithms to solve the SAT problem that attempt to contain the growth of BDD-size while identifying solutions quickly. The first algorithm, called BSAT, is a recursive, backtracking algorithm that uses an exhaustive search to find a SAT solution. The well known unate recursive paradigm is exploited to solve the SAT problem. The second algorithm, called INCOMPLETE-SEARCHUSAT (abbreviated IS-USAT), incorporates an incomplete search to find a solution. The search is incomplete inasmuch as it is restricted to only those regions that have a high likelihood of containing the solution, discarding the rest. Using our techniques we were able to find SAT solutions not only for all MCNC & ISCAS benchmarks, but also for a variety of industry standard designs.

this paper we survey some state-of-the-art techniques used to perform automatic verification of combinational circuits. We classify the current approaches for combinational verification into two categories: functional and structural. The functional methods consist of representing a circuit as a canonical decision diagram. Two circuits are equivalent if and only if their decision diagrams are equal. The structural methods consist of identifying related nodes in the circuit and using them to simplify the problem of verification. We briefly describe some of the methods in both the categories and discuss their merits and drawbacks.