This article introduces the concept of combining both form (CAD models) and behavior (simulation models) of mechatronic system components into component objects. By connecting these component objects to each other through their ports, designers can create both a systemlevel design description and a virtual prototype of the system. This virtual prototype, in turn, can provide immediate feedback about design decisions by evaluating whether the functional requirements are met in simulation. To achieve the composition of behavioral models, we introduce a port-based modeling paradigm. The port-based models are reconfigurable, so that the same physical component can be simulated at multiple levels of detail without having to modify the system-level model description. This allows the virtual prototype to evolve during the design process and to achieve the accuracy required for the simulation experiments at each design stage. To maintain the consistency between the form and behavior of compone...

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Abstract—This paper addresses the problem of converting a conventional video stream based on sequences of frames into the spike event-based representation known as the address-event-representation (AER). In this paper we concentrate on rate-coded AER. The problem is addressed as an algorithmic problem, in which different methods are proposed, implemented and tested through software algorithms. The proposed algorithms are comparatively evaluated according to different criteria. Emphasis is put on the potential of such algorithms for a) doing the frame-based to event-based representation in real time, and b) that the resulting event streams ressemble as much as possible those generated naturally by rate-coded address-event VLSI chips, such as silicon AER retinae. It is found that simple and straightforward algorithms tend to have high potential for real time but produce event distributions that differ considerably from those obtained in AER VLSI chips. On the other hand, sophisticated algorithms that yield better event distributions are not efficient for real time operations. The methods based on linear-feedback-shift-register (LFSR) pseudorandom number generation is a good compromise, which is feasible for real time and yield reasonably well distributed events in time. Our software experiments, on a 1.6-GHz Pentium IV, show that at 50 % AER bus load the proposed algorithms require between 0.011 and 1.14 ms per 8 bit-pixel per frame. One of the proposed LFSR methods is implemented in real time hardware using a prototyping board that includes a VirtexE 300 FPGA. The demonstration hardware is capable of transforming frames of 64 64 pixels of 8-bit depth at a frame rate of 25 frames per second, producing spike events at a peak rate of IH U events per second. I.

Analogical reasoning plays an important role in design. In particular, cross-domain analogies appear to be important in innovative and creative design. However, making cross-domain analogies is hard and often requires abstractions common to the source and target domains. Recent work in case-based design suggests that generic mechanisms are one type of abstractions useful in adapting past designs. However, one important yet unexplored issue is where these generic mechanisms come from. We hypothesize that they are acquired incrementally from design experiences in familiar domains by generalization over patterns of regularity. Three important issues in generalization from experiences are what to generalize from an experience, how far to generalize, and what methods to use. In this paper, we describe how structure-behaviorfunction models of designs in a familiar domain provide the content, and togetherwith the problem-solving context in which learning occurs, also provide the constraints for learning generic mechanisms from design experiences. In particular, we describe the model-based learning method with a scenario of learning of feedback mechanism.

When a bright light source is viewed through Night Vision Goggles (NVG), the image of the source can appear enveloped in a “halo ” that is much larger than the “weak-signal ” point spread function of the NVG. The halo phenomenon was investigated in order to produce an accurate model of NVG performance for use in psychophysical experiments. Halos were created and measured under controlled laboratory conditions using representative Generation III NVGs. To quantitatively measure halo characteristics, the NVG eyepiece was replaced by a CMOS imager. Halo size and intensity were determined from camera images as functions of point-source intensity and ambient scene illumination. Halo images were captured over a wide range of source radiances (7 orders of magnitude) and then processed with standard analysis tools to yield spot characteristics. The spot characteristics were analyzed to verify our proposed parametric model of NVG halo event formation. The model considered the potential effects of many subsystems of the NVG in the generation of halo: objective lens, photocathode, image intensifier, fluorescent screen and image guide. A description of the halo effects and the model parameters are contained in this work, along with a qualitative rationale for some of the parameter choices.

This thesis was presented by

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Introduction Power consumption is an increasingly important issue in general purpose processors, particularly in the mobile computing segment. In present processors, most of the power dissipation is dynamic power dissipation, which arises due to signal transitions. Various techniques have been studied and implemented to reduce dynamic power dissipation, including clock gating, cache sub-banking, voltage scaling, and eliminating needless computation (these techniques are directly relevant to computer architects). However, as transistors become smaller and faster, static power (also called leakage power) dissipation will become increasingly significant. Technology scaling is increasing both the absolute and relative contributions of static power dissipation. Looking at current technology trends, it is evident that static power dissipation is growing at a faster rate than dynamic power dissipation. In just a few processor generations, the curves will intersect. Using scaling th

Leakage power minimization has become an important issue with technology scaling. Variable threshold voltage schemes have become popular for standby power reduction. In this work we look at another emerging aspect of this potent prob-lem which is leakage power reduction in active mode of op-eration. In gate level circuits, a large number of gates are not switching in active mode at any given point in time but nevertheless are consuming leakage power. We propose n fine-grained Forward Body Biasing (FBB) Scheme for active mode leakage power reduction in gate level circuits without any delay penalty. Our results show that our optimal poly-nomial time FBB allocation scheme results zn 70.2 % reduc-tion in leakage currents. We also present a novel placement-driven FBB allocation algorithm that effectively reduces the area penalty using the post-placement area slack and results in 39.7%, 64.7 % and 67.1 % reduction in leakage currents for 0%, 4 % and 8 % area slack respectiuely.

Recent applications of magnetoelectronic devices have revolutionized the semiconductor and elec-tronic industries. The discovery of new magnetoelectronic devices has led to the development of new magnetic field sensors, read heads for magnetic hard drives, and MRAM technology. Although magnetoelectronic devices have found particular success in these areas, little work has been done in demonstrating the potential of using these devices for digital logic. In this thesis, we present novel circuit designs for magnetoelectronic gate structures. We propose designs that alleviate the intrinsic power consumption required by these devices. We also address the issue of process vari-ation by proposing reliable circuit designs for magnetoelectronic gates. Lastly, we demonstrate a particular application of magnetoelectronic gates by realizing non-volatile reconfigurable threshold logic, which can be used to implement a fully reprogrammable macrocell. iii To my father, mother, and sister iv ACKNOWLEDGMENTS