....................................... x 1 INTRODUCTION . . . . . . ........................... 1 1.1 Optimization framework ........................... 1 1.2 Measurements................................. 2 1.3 Overview ................................... 2 2 BACKGROUND .................................. 3 2.1 Controlflowgraphs.............................. 3 2.1.1 Dominators . . . ........................... 3 2.1.2 Loops . . . . . . ........................... 4 2.2 Staticsingleassignmentform......................... 6 2.2.1 Construction . . ........................... 7 2.2.2 Destruction . . . ........................... 11 2.3 Partial redundancy elimination . . . . .................... 12 2.3.1 SSAPRE . . . . ........................... 12 2.4 Other optimizations . . . ........................... 14 2.5 Typebasedaliasanalysis........................... 15 2.5.1 Terminology and notation . . .................... 16 v Page 2.5.2 TBAA . . . . . . ........................

The performance of the input/output subsystem is becoming increasingly important for many applications. Commercial I/O intensive applications are a fast growing market segment and experience constantly increasing performance demands. Many of these applications exploit concurrency to overlap the latency of I/O operations to improve throughput. At the same time, semiconductor technology trends result in a growing gap between application and operating system performance. Consequently, operating system overhead increasingly limits the efficiency of latency-hiding techniques to improve throughput. This dissertation develops and evaluates a novel I/O architecture that, by providing user-level access to the I/O subsystem, minimizes I/O overhead while maintaining the level of protection and programming flexibility of conventional kernel-based architectures. Inexpensive hardware mechanisms in the I/O device and host processor implement protected user-level request initiation, user-space data transfers, and user-level notifications. Together, these mechanisms are able to reduce I/O overhead by up to two orders of magnitude. As a result, applications are able to efficiently overlap long-latency I/O operations to maximize throughput and to exploit the scalable bandwidth of next-generation distributed I/O architectures. The flexibility of the basic mechanisms facilitates library implementations of a variety of standard I/O programming models with low overhead, as the architecture does not restrict the allocation and use of I/O buffers.