Register files represent a substantial portion of the energy budget in modern processors, and are growing rapidly with the trend towards larger Instruction Level Parallelism (ILP). The energy cost of a register file access depends greatly on the register file circuitry used. This paper compares various register file circuitry techniques for their energy efficiencies, as a function of the architectural parameters such as the number of registers and the number of ports. The Port Priority Selection technique combined with differential reads and low-swing writes was found to be the most energy efficient and provided significant energy savings compared to traditional approaches in the case of large register files. The dependence of register file access energy upon technology scaling is also studied. However, as this paper shows, it appears that none of these will be enough to prevent centralized register files from becoming the dominant power component of next-generation superscalar compute...

¾¾ A 3-transistor nonvolatile analog storage cell with 14 bits effective resolution and railto -rail buffered voltage output is presented. The memory, which consists of charge stored on a MOS transistor floating gate, is written by means of hotelectron injection and erased by means of gate oxide tunneling. The circuit allows simultaneous memory reading and writing; by writing the memory under feedback control, errors due to oxide mismatch or trapping can be nearly eliminated. Small size and low power consumption make the cell especially attractive for use in analog neural networks. The cell is fabricated in a 2 µm n-well silicon BiCMOS process available from MOSIS. I. INTRODUCTION NE IMPEDIMENT to the development of silicon neural networks is the difficulty in storing analog weight values on-chip. Prior efforts typically used capacitive storage with clocked refresh [1], or multi-bit digital storage [2]. Both approaches pay a large penalty in terms of cell size, complexity, resolution,...

As semiconductor technology enters the deep submicron era, reliability has become a major challenge in the design and manufacturing of next generation VLSI circuits. In this paper we focus on one reliability issue - the antenna effect in the context of 3-layer channel routing. We first present an antenna effect model in 3-layer channel routing and, based on this, an antenna effect cost function is proposed. A layer reassignment approach is adopted to minimize this cost function and we show that the layer reassignment problem can be formulated as a network bipartitioning problem. Experimental results show that the antenna effect can be reduced considerably by applying the proposed technique. Compared with previous work, one advantage of our approach is that no extra channel area is required for antenna effect minimization. We show that layer reassignment technique can be used in yield-related critical area minimization in 3-layer channel routing as well. The trade-off between these two ...

CONTENTS ACKNOWLEDGMENTS ..................................................................................... v LIST OF TABLES................................................................................................ vi LIST OF FIGURES ............................................................................................vii SUMMARY............................................................................................................. x Chapter I. INTRODUCTION .........................................................................1 Chapter II. BACKGROUND AND SYSTEM REQUIREMENT ................7 2.1 Background .....................................................................................7 2.2 System Requirements...................................................................24 Chapter III. A SCALEABLE CMOS CURRENT-MODE PREAMPLIFIER DESIGN AND INTEGRATION...............32 3.1 Introdu

Recent papers reporting CMOS RF building blocks have aroused great expectations for RF receivers using deepsubmicron technologies. This paper examines the trend in CMOS scaling, in order to establish the required current levels and achievable performance for different feature sizes, if robust, easily manufacturable designs are to be implemented for cellular applications. The boundary conditions (system-level constraints) for such designs, in terms of the number of trimmed and untrimmed external components and the roles they play in relaxing active circuit requirements, are emphasized throughout to make comparison of active RF circuits meaningful. At 1 GHz, 0.25- m CMOS appears to be the threshold for robust, low-NF RF front ends with current consumption competitive with today's BJT implementations. Index Terms---CMOS RF, low-noise amplifier, low-power design, mixer, prescaler, RF-IC, technology scaling, wireless communication. I. INTRODUCTION S CALING of CMOS technologies has defie...

As semiconductor devices enter the deep sub-micron era, reliability has become a major issue and challenge in VLSI design. Among all the failure mechanisms, hot-carrier effect is one of those which have the most significant impact on the long-term reliability of high-density VLSI circuits. In this paper, we address the problem of minimizing hot-carrier effect during the technology mapping stage of VLSI logic synthesis. We first present a logic-level hot-carrier model, and then, based on this model, we propose a technology mapping algorithm for hot-carrier effect minimization. The proposed algorithm has been implemented in the framework of the Berkeley logic optimization package SIS. Our results show that an average of 29.1% decrease in hot-carrier effect can be achieved by carefully choosing logic gates from cell libraries to implement given logic functions for a set of benchmarks. It has also been observed that the best design for hot-carrier effect minimization does not necessarily c...

This paper introduces Architecture Evaluator's Workbench(AEWB), a high level design space exploration methodology, and its application to floating point units(FPUs). In applying AEWB to FPUs, a metric for optimizing and comparing floating point unit implementation is developed. The metric -- FUPA incorporates four aspects of AEWB -- latency, cost, technology and profiles of target applications. FUPA models latency in terms of delay, cost in terms of area, and profile in terms of percentage of different floating point operations. We utilize sub-micron device models, interconnect models, and actual microprocessor scaling data to develop models used to normalize both latency and area enabling technology-independent comparison of implementations. This report also surveyed most of the state of the art microprocessors, and compared them utilizing FUPA. Finally, we correlate the FUPA results to reported SPECfp92 results, and demonstrate the effect of circuit density on FUPA implementations. ...

We have designed a process-insensitive preamplifier for an optical receiver, fabricated it in several different minimum feature sizes of standard digital CMOS, and demonstrated design scaleability of this analog integrated circuit design. The same amplifier was fabricated in a 1.2 µm and two different 0.8 µm processes through the MOSIS foundry [1]. The amplifier uses a multi-stage, low-gain-per-stage approach. It has a total of 5 identical cascaded stages. Each stage is essentially a current mirror with a current gain of 3. Three of these preamplifiers have been integrated with a GaAs Metal-Semiconductor-Metal (MSM) photodetector and one with an InGaAs MSM detector by using a thin-film epilayer device separation and bonding technology [2]. This quasi-monolithic front-end of an optical receiver virtually eliminates the parasitics between the photodetector and the silicon CMOS preamplifier. We have demonstrated speed and power dissipation improvement as the minimum feature size of the transistors shrink.

This thesis deals with several aspects of the utilization of finite (Galois) fields in multiplevalued logic (MVL). Current-mode CMOS circuits are proposed that realize operations in Galois fields with four elements. A synthesis technique with such circuits and a transform method are presented; they are based on the Galois field polynomial representation. Methods for obtaining such representations are discussed in two steps, dealing with one-dimensional and multidimensional cases separately. A new method is developed for representation of single variable functions. It is limited to fields of small sizes (2 to 4), which is acceptable because only these fields are readily implementable with today's MVL technology. The method provides a natural way of dealing with incompletely specified functions and has better computational properties than other similar methods. A natural extension of the method to the multidimensional case is derived. The multidimensional representation algorithm has all...

Introduction 4.2 A First Glance 4.3 Interconnect Parameters --- Capacitance, Resistance, and Inductance 4.3.1 Capacitance 4.3.2 Resistance 4.3.3 Inductance 4.4 Electrical Wire Models 4.4.1 The Ideal Wire 4.4.2 The Lumped Model 4.4.3 The Lumped RC model 4.4.4 The Distributed rc Line 4.4.5 The Transmission Line 4.5 SPICE Wire Models 4.5.1 Distributed rc Lines in SPICE 4.5.2 Transmission Line Models in SPICE 4.6 Perspective: A Look into the Future chapter4.fm Page 103 Monday, September 6, 1999 1:44 PM 104 THE WIRE Chapter 4 4.1Introduction Throughout most of the past history of integrated circuits, on-chip interconnect wires were considered to be second class citizens that had only to be considered in special cases or when performing high-precision analysis. With the introduction of deep-submicron semiconductor technologies, this picture is undergoing rapid changes. The parasitics effects introduced by the wires displ