Deep packet processing is migrating to the edges of service provider networks to simplify and speed up core functions. On the other hand, the cores of such networks are migrating to the switching of high-speed traffic aggregates, e.g., using switching with dense wavelength division multiplexing (DWDM). As a result, more services will need to be performed at the edges, both on behalf of the core and end users. Associated network equipment will therefore require high flexibility to support evolving high-level services as well as extraordinary performance to deal with the high packet rates. Whereas in the past network equipment were based either on general-purpose processors (GPPs) or application-specific integrated circuits (ASICs), favoring flexibility over speed or vice versa, the network processor approach achieves both flexibility and performance. The key advantage of network processors is that hardware-level performance is complemented by flexible software architecture. In this paper, we describe the IBM PowerNP&tm; NP4GS3 network processor and how it addresses these issues. Its hardware and software design characteristics and its comprehensive base operating software of this network processor make it well suited for a wide range of networking applications.

We present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Many Network Processors employ hardware accelerators for implementing key domain-specific tasks. New applications require new tasks, such as pattern matching, to be performed on network packets in real-time. Using our proposed accelerator, we have implemented several such tasks and measured their performance. The accelerator achieves up to 25-fold improvement on the performance of pattern matching, and 12-fold improvement for tree lookup when compared to optimized software solutions. We present delay, area and power requirements of the accelerator for an ASIC design. We also present a recoffigurable design of the accelerator and present a comparison between these implementations. Since the accelerator can be used for different tasks, the hardware requirements are small compared to an accelerator group that implements the same set of tasks. We also present accurate analytic models to estimate the execution time of these networking tasks.

Abstract—This paper suggests a new approach for bitstream processing of embedded systems, using a combination of C++ metaprogramming combined with architecture extensions of an customizable embedded processor. Firstly, by using C++ metaprogramming techniques, we are able to code application software that needs to manipulate bitstreams in a very compact manner. Secondly, by using the architecture extensions of the Tensilica embedded processor indirectly via C++ operator overloading, the application code can seamlessly exploit custom architecture extensions. The intention is to do bitstream related processing with low programming effort, while generating runtime efficient code. Compared to other bitstream processing approaches we require no compiler modifications to exploit custom architecture features. Rather we put the bitstream related manipulation functionality into an active library, generated by a C++ metaprogram. I.