... This paper introduces the reader to various aspects of co-design. We highlight the commonalities and point out the differences in various co-design problems in some application areas. Co-design issues and their relationship to classical system implementation tasks are discussed to help the reader develop a perspective on modern digital system design that relies on computer-aided design (CAD) tools and methods.

Designers of distributed embedded systems face many challenges in determining the tradeoffs when defining a system architecture or retargeting an existing design. Communication synthesis, the automatic generation of the necessary software and hardware for system components to exchange data, is required to more effectively explore the design space and automate very error-prone tasks. This paper examines the problem of mapping a high-level specification to an arbitrary architecture that uses specific, common bus protocols for interprocessor communication. The communication model presented allows for easy retargeting to different bus topologies, protocols, and illustrates that global considerations are required to achieve a correct implementation. An algorithm is presented that partitions multihop communication timing constraints to effectively utilize the bus bandwidth along a message path. The communication synthesis tool is integrated with a system co-simulator to provide performance data for a given mapping.

Dynamically reconfigurable embedded systems (DRESs) target an architecture consisting of generalpurpose processors and field programmable gate arrays (FPGAs), in which FPGAs can be reconfigured in run-time to achieve cost saving.

In order to automate design reuse, methods for composing system components must be developed. The goal of this research is to automate the process of generating interfaces between hardware subsystems. The algorithms presented here can be used to generate a cycle-accurate, synchronous interface between two hardware subsystems given an HDL model of each subsystem. These algorithms have been implemented in the POLARIS hardware composition tool and have been used to generate an interface between a MIPS microprocessor and the SRAM that comprises its secondary cache. Interface generation for the MIPS R4000 is described. 1. Introduction The increasing complexity of electronic systems is forcing designers to consider, if not implement, design reuse and intellectual property sharing. As this methodology matures, a new breed of tools will be required to automate component selection, subsystem scheduling, and system composition. This paper presents a mechanism for composing hardware blocks that...

This paper discusses the use of C for the design of digital systems. The paper distinguishes a number of different approaches towards the use of programming languages for digital system design and will discuss in more detail how C can be used for system modeling and refinement, for simulation, and for architecture design.

As designers may model mixed hardware--software systems using a subset of or ++, we present SpC, a solution to synthesize and optimize hardware models with pointers. In hardware, a pointer is not only the address of data in memory, but it may also reference data mapped to registers, ports, or wires. Pointer analysis is used to find the set of locations each pointer may reference in a program at compile time. In this paper, we address the problem of synthesizing and optimizing pointers to multiple variables or array elements. The value of the pointers are encoded and branching statements are used to dynamically access data referenced by pointers. A heuristic is used to efficiently encode the values of the pointers. Compiler techniques are also used to reduce storage before loads and stores. An implementation using the SUIF framework (Wilson et al., 1994; SUIF Compiler Framework) is presented, followed by some case studies and experimental results.

The key issue in the design of Systems-on-a-Chip (SoC) is to trade-off efficiency against flexibility, and time to market versus cost. Current deep submicron processing technologies enable integration of multiple software programmable processors (e.g. CPUs, DSPs) and dedicated hardware components into a single cost-efficient IC. Our top-down design methodology with various abstraction levels helps designing these ICs in a reasonable amount of time. This methodology starts with a high-level executable specification, and converges towards a silicon implementation. A major task in the design process is to ensure that all components (hardware and software) communicate with each other correctly. In this article, we tackle this problem in the context of the signal processing domain in two ways: we propose a modular, flexible, and scalable heterogeneous multi-processor architecture template based on distributed shared memory, and we present an efficient and transparent protocol for communication and (re)configuration. The protocol implementations have been incorporated in libraries, which allows quick traversal of the various abstraction levels, so enabling incremental design. The design decisions to be taken at each abstraction level are evaluated by means of (co-)simulation. Prototyping is used too, to verify the system's functional correctness. The effectiveness of our approach is illustrated by a design case of a multi-standard video and image codec.

Virtually every system designed today is an amalgam of hardware and software. Unfortunately, software and circuits that communicate across the hardware/software boundary are tedious and error-prone to create. This suggests a more automatic way to synthesize them. This paper presents the shim language, which combines imperative C-like semantics for software and rtl-like semantics for hardware to allow a unified description of hardware/software systems. Hardware processes and software functions communicate through shared variables, hardware for which is automatically synthesized by the shim compiler, which generates C and synthesizable vhdl. I demonstrate the effectiveness of the language by re-implementing an I 2 C bus controller. The shim source is half the size of an equivalent manual implementation, slightly faster, and has a smaller memory footprint. Partial and complete hardware implementations in shim are also presented, showing that shim is succinct and effective. Key words: Hardware-software codesign, language design, interface synthesis

This dissertation presents methods for automating the synthesis of embedded systems, i.e., special-purpose computers. In addition, it describes a method for analyzing the manner in which real-time operating system use influences embedded system power consumption.

Interface synthesis seeks to automate the process of interconnecting components. There are many levels of interconnection that must be considered including electrical, power, logic, register-transfer, device drivers, and higher software levels. This presentation will cover a vertical slice of the interfacing problem from digital logic up to coordinating communications between software components. The focus will be within an embedded systems context where the interfacing is between processors and memory and peripheral blocks as is the case in system-on-a-chip design. The structure of the tutorial will parallel the history of CAD efforts in this area. We will begin with the early work in interface specification and logic synthesis then proceed on to the problems of interconnecting hardware to processors and their software, and finish with purely software interfaces involving inter-process communication and protocols between multiple processors. At each level we will discuss specification, synthesis, and verification aspects as well as highlight the currently available tools and on-going research efforts. Keywords interface synthesis, bus protocols, component-based design, intellectual property, design abstraction, design re-use, interprocess communication Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.