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12
A CADoriented modeling approach of frequencydependent behavior of substrate noise coupling for mixedsignal IC design
 in Proc. IEEE Int. Symp. Quality Electronic Design
, 2003
"... A simple, efficient CADoriented equivalent circuit modeling approach of frequencydependent behavior of substrate noise coupling is presented. It is shown that the substrate exhibits significant frequencydependent characteristics for high frequency applications using epitaxial layers on a highly d ..."
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A simple, efficient CADoriented equivalent circuit modeling approach of frequencydependent behavior of substrate noise coupling is presented. It is shown that the substrate exhibits significant frequencydependent characteristics for high frequency applications using epitaxial layers on a highly doped substrate. Using the proposed modeling approach, circuit topographies consisting of only ideal lumped circuit elements can be synthesized to accurately represent the frequency response using yparameters. The proposed model is wellsuited for use in standard circuit simulators. The extracted model is shown to be in good agreement with rigorous 3D device simulation results. 1.
Analyzing the Impact of Substrate Noise on Embedded AnalogtoDigital Converters
, 2002
"... This paper presents the analysis and measurements of the impact of digital substrate noise on embedded AnalogtoDigital converters. The impact of substrate noise on analog design is explained, followed by a specific entire impact analysis of the impact on a regenerative comparator and an A/D conver ..."
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Cited by 5 (0 self)
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This paper presents the analysis and measurements of the impact of digital substrate noise on embedded AnalogtoDigital converters. The impact of substrate noise on analog design is explained, followed by a specific entire impact analysis of the impact on a regenerative comparator and an A/D converter. To confirm the analysis the substrate noise has also been measured on a test chip designed in a 0.35 m heavilydopedsubstrate CMOS technology. From the measurements it was deduced that SNR and the effective number of bits are reduced by 20%.
Digital circuit capacitance and switching analysis for ground bounce in IC’s with a highohmic substrate
 in Proc. Eur. SolidState Circuits Conf
, 2003
"... Abstract—Substrate noise is a major obstacle for mixedsignal integration. Ground bounce is a major contributor to substrate noise generation due to the resonance caused by the inductance and the admittance that consists of the onchip digital circuit capacitance of the MOS transistors, the decoupl ..."
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Abstract—Substrate noise is a major obstacle for mixedsignal integration. Ground bounce is a major contributor to substrate noise generation due to the resonance caused by the inductance and the admittance that consists of the onchip digital circuit capacitance of the MOS transistors, the decoupling, and the parasitics arising from the interconnect. In this paper, we address: 1) the dependence of the admittance on the different states of the circuit, the supply voltage, and the interconnect, and 2) the computation of the total supply current with ground bounce. By using a fast and accurate macromodeling approach, the admittances of several test circuits are computed with 2%–3 % error relative to the values simulated from the complete SPICE level netlist, but several orders of magnitude faster in CPU time and with 10 % maximum error relative to the measurements on a test ASIC fabricated in a 0.18 m CMOS process on a highohmic substrate with 18 cm resistivity. The measurements also show that this admittance mainly depends only on the connectivity of the gates to the supply rail rather than their connectivity among each other. Index Terms—Crosstalk, decoupling, integrated circuit modeling, MOS capacitors, mixed analog–digital ICs, power distribution, substrate noise, systemonachip. I.
THE SUBSTRATE NOISE DETECTOR FOR NOISE TOLERANT
"... Abstract—Substrate noise is an important parasitic of mixedsignal integrated circuits. The existing analysis tools of substrate noise provide accuracy but need complex calculation to model the substrate noise. Also the model can be used as a guidance for optimal placement and routing. In this paper ..."
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Abstract—Substrate noise is an important parasitic of mixedsignal integrated circuits. The existing analysis tools of substrate noise provide accuracy but need complex calculation to model the substrate noise. Also the model can be used as a guidance for optimal placement and routing. In this paper, a new type of substrate noise detector is proposed. It is embedded in a mixedsignal IC and monitors the level of substrate noise. The voltage comparators are used to detect errors and a counter tracks the number of errors periodically. From the number of error, the level of substrate noise is estimated using the probabilistic approach. This type of detector is useful in that it monitors substrate noise in realtime. Using this, the various adaptive algorithms become feasible to reduce substrate noise. The details of detector circuits are given and adaptive analogtodigital converter as an application is discussed in this paper. Index Terms—IC, mixed signals, sustrate noise, TIQ
Modeling Impact of Digital Substrate Noise on Embedded Regenerative Comparators
"... Abstract — This paper presents an analysis and highlevel modeling method used to estimate the impact of digital substrate noise on a CMOS regenerative comparator embedded in a mixedsignal environment. A test chip was designed in a 0.35 m heavily doped substrate technology, in order to measure the ..."
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Abstract — This paper presents an analysis and highlevel modeling method used to estimate the impact of digital substrate noise on a CMOS regenerative comparator embedded in a mixedsignal environment. A test chip was designed in a 0.35 m heavily doped substrate technology, in order to measure the impact of digital noise on embedded CMOS regenerative comparators. Secondly an efficient equationbased model of the impact of the digital substrate noise on embedded CMOS regenerative comparators was derived. It is based on the statistical analysis of the jitter measured at the output of the comparator. I.
Substrate Noise Analysis and Experimental Verification for the Efficient Noise Prediction of a Digital PLL
"... Abstract — Substrate noise is a major impediment to mixedsignal integration. This paper describes a CAD tool that can be used at any stage of the design cycle to estimate the substrate noise generated by large digital circuits. The results have been verified with substrate noise measurements on a 48 ..."
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Abstract — Substrate noise is a major impediment to mixedsignal integration. This paper describes a CAD tool that can be used at any stage of the design cycle to estimate the substrate noise generated by large digital circuits. The results have been verified with substrate noise measurements on a 480 MHz digital PLL implemented in a 90 nm CMOS process on a high resistivity substrate. Keywords: substrate noise, mixedsignal simulation, computer aided design I.
3) On the average, the error of BELT compared to VG4 is 5.2%;
"... while on the average, the VG4 delay is almost a factor of three higher than that predicted by ELT. 4) Compared to SPICEbased VG4, the error of BELT is 9 % on the average. These experiments illustrate that our estimation technique is sufficiently accurate for design planning, while ignoring the bloc ..."
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while on the average, the VG4 delay is almost a factor of three higher than that predicted by ELT. 4) Compared to SPICEbased VG4, the error of BELT is 9 % on the average. These experiments illustrate that our estimation technique is sufficiently accurate for design planning, while ignoring the blockages is prohibitively costly. Finally, we note how efficient the estimation technique is. The total runtime in seconds for running the 13 test cases mentioned above was 0.24, 23.0, and 29.0 for BELT, VG1, and VG4, respectively. In other words, BELT is about 100 times faster than running an actual bufferinsertion algorithm. For medium sized nets such as n786 and n869, the runtime of VG4 plus the SPICE simulation is over 10 000 times slower than the runtime of BELT. VI. CONCLUSION We presented closedform formulas for estimating the achievable buffered delay when buffering restrictions exist in the layout. We demonstrated that adding blockages to the layout could cause significant error in estimation techniques that ignore the blockage terrain. We also showed that our technique is a lower bound, has an error of less than one percent for twopin nets, and has only a few percent error for multisink nets.
Trend and Challenge on SystemonaChip Designs
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS 1 Analysis of the PLL Jitter Due to Power/Ground and Substrate Noise
"... and mixed analogdigital integrated circuits experience substrate coupling due to the simultaneous circuit switching and power/ground (P/G) noise which translate to a timing jitter. In this paper. an analysis of the PLL timing jitter due to substrate noise resulting from P/G noise and largesignal s ..."
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and mixed analogdigital integrated circuits experience substrate coupling due to the simultaneous circuit switching and power/ground (P/G) noise which translate to a timing jitter. In this paper. an analysis of the PLL timing jitter due to substrate noise resulting from P/G noise and largesignal switching is presented. A general comprehensive stochastic model of the substrate and P/G noise sources in very largescale integration circuits is proposed. This is followed by calculation of the phase noise of the constituent voltagecontrolled oscillator (VCO) in terms of the statistical properties of substrate and P/G noise. The PLL timing jitter is then predicted in response to the VCO phase noise. Our mathematical method is utilized to study the jitterinduced P/G noise in a CMOS PLL, which is designed and simulated in a 0.25 m standard CMOS process. A comparison between the results obtained by our mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model. Index Terms—Cyclostationary noise, jitter, phaselocked loop (PLL), phase noise, power/ground bounce, random process, ring oscillator, substrate noise, voltagecontrolled oscillator (VCO). I.