We present a syntactic theory for the behavioral subset of the Verilog Hardware Description Language. Due to the complexity of the language, the construction of this theory represents a serious test of the suitability of syntactic operational techniques for reasoning about industrial languages. Overall, we have found that these techniques are rather robust but with a few caveats. Our theory formalizes the simulation cycle explicitly, exposes a number of ambiguities and inconsistencies in the language reference manual (LRM), and is the most accurate known description of this subset of Verilog, with respect to the LRM. The syntactic theory has been used to automatically derive a simulator for Verilog. 1 Introduction Programming calculi, which concentrate on a small set of constructs that capture the "essence" of a language, commonly come equipped with syntactic theories that explain, in intuitive yet formal terms, the evaluation and optimization of programs. In principle, then, the deve...

My thanks first of all to my advisor, Dr.Amr Sabry. Without his exceptional inspiration and guidance, as well as the occasional kick in the pants (much needed), this project would not exist. Thanks to Steven Sharp and Steve Meyer for their helpful correspondences and explanation of Verilog semantics. And thanks to the members of the Internet Verilog community of comp.lang.verilog who participated in my nonblocking assignment experiment—Hitesh Brahmbhatt, Larice Robert, Magnus Soderberg, Edward Arthur, and Robert Szczygiel. Thank you to Daryl Stewart for reading this work, and for finding two small (but important) bugs. Finally, a huge thank you to Janet, my life partner and closest friend—for being there. Dedication To my parents, who taught me to look, Bob Horn, who taught me how, and to Janet, who helped me to know what I saw.

Predicate abstraction has been widely used for model checking hardware/software systems. However, for control intensive systems, existing predicate abstraction techniques can potentially result in a blowup of the size of the abstract model. We deal with this problem by retaining important control variables in the abstract model. By this method we avoid having to introduce an unreasonable number of predicates to simulate the behavior of the control variables. We also show how to improve predicate abstraction by extracting useful information from a high level representation of hardware/software systems. This technique works by first extracting relevant branch conditions. These branch conditions are used to invalidate spurious abstract counterexamples through a new counterexample-based lazy refinement algorithm. Experimental results are included to demonstrate the effectiveness of our methods.

An elementary theory is proposed for reasoning about circuits at the timed level. Its relationship to traditional differential calculus is explored; it is applied to the analysis of circuits with feedback; and algorithms for detection of transients and hazards are given. Finally a small case study, of a positive-edge-triggered register, is presented. Emphasis is on the use of laws which draw on the intuition gained from traditional dierential calculus. Key words: formal methods; signal; hazard analysis; timing. 1

This paper considers how the algebraic semantics for Verilog relates with its denotational semantics. Our approach is to derive the denotational semantics from the algebraic semantics. We first present the algebraic laws for Verilog. Every program can be expressed as a guarded choice that can model the execution of a program. In order to investigate the parallel expansion laws, a sequence is introduced, which indicates the instantaneous action is due to which exact parallel component. A normal form is defined for each program by using the locality sequence. We provide a strategy for deriving the denotational semantics based on the algebraic normal form. Using the strategy, the denotational semantics for every program can be calculated. Program equivalence can also be explored by using the derived denotational semantics. 1

An operational semantics for a significant subset of the Verilog Hardware Description Language (HDL) has been developed. An unusual aspect of the semantics is that it was formulated as a Prolog logic program. This allows the possibility of simulating the semantics. In addition, a literate programming style has been used, so the semantics can be processed by the LaTeX document preparation system with minimal and fully automated preprocessing. Bringing together the paradigms of operational semantics, logic programming and literate programming in this manner has proved a great aid in a number of ways. It has helped improve the understanding of the semantics, in the formalization of semantic aspects left informal in the original mathematical formulation of the semantics, and in the maintenance of the formal semantics and its associated informal description.

Reconfigurable logic devices such as the FPGA have brought about a revolution in the field of hardware design. The reduction in development costs has had a huge impact on broadening the scope of applications for which a hardware implementation is a realistic possibility. Current FPGA devices run to many millions of gates, giving a huge potential for efficiency gains, benefiting from the inherently parallel nature of hardware circuits. These devices continue to grow in size, to the end that we can now seriously consider implementing even large scale systems purely in reconfigurable logic. Despite these advances, we find ourselves somewhat lacking in the tools and methodologies required to fully exploit this potential. Issues of hardware implementation and parallelism intro-duce significant complexity into the design process. We argue that without the correct approach, not only will this potential be under used, but the inherent complexity will undermine people’s

This paper presents a denotational semantics for the hardware description language Verilog using Duration Calculus. The language contains interesting features such as event-driven process, shared-variable concurrency and simulator-based description. We examine algebraic properties of Verilog, which can be used in support of program simplification and optimisation. To covert programs to normal form, we enrich the language with guarded choice and composite guard. Zhu Huibiao is a Fellow of UNU/IIST, on leave of absence from Department of Computer Science, East China Normal University, Shanghai, where he is a lecturer. E-mail: zhb@iist.unu.edu Copyright c fl 2000 by UNU/IIST, Zhu Huibiao and He Jifeng Contents i Contents 1 Introduction 1 2 The Semantical Model of Verilog 2 2.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 Observation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Sequential Constructs...

eated a pipelined, multi-issue design. It includes Tomasulo's algorithm, memory-write buffering, loadbypassing, external and internal exceptions, a branch prediction mechanism, speculative execution, and privileged instructions, and permits the self-modification of program code. We included these features to ensure that we had specified a system containing a number of the features commonly found in modern microprocessor designs. Using the ACL2 logic, we specified this design both at a microarchitectural (MA) level, where all of the features just mentioned are apparent, and at the instruction-set (ISA) level, where only the instruction set is specified. Using the ACL2 theorem-proving system, we mechanically proved that the MA description implemented the ISA specification. Using formal techniques as an aid in hardware design is spreading. 2-4 The precision of using formal techniques can improve the Warren A. Hunt, Jr. IBM Austin Research Laboratory

Verilog is a Hardware Description Language used for the design and description of hardware in a behavioral and structural way. It has some interesting features like concurrency, synchronism, shared variables, non-blocking assignments (scheduled assignments), timing controls, infinite computations, zero-time computations, etc., that makes it an interesting language to study. This report explains some features of Verilog in an informal way through small examples and presents the Verilog code of STARI as a main application. Copyright c fl 1998 by UNU/IIST, Pablo Giambiagi and Gerardo Schneider Contents i Contents 1