Since they often embody compact but mathematically sophisticated algorithms, operations for computing the common transcendental functions in floating point arithmetic seem good targets for formal verification using a mechanical theorem prover. We discuss some of the general issues that arise in verifications of this class, and then present a machine-checked verification of an algorithm for computing the exponential function in IEEE-754 standard binary floating point arithmetic. We confirm (indeed strengthen) the main result of a previously published error analysis, though we uncover a minor error in the hand proof and are forced to confront several subtle issues that might easily be overlooked informally. The development described here includes, apart from the proof itself, a formalization of IEEE arithmetic, a mathematical semantics for the programming language in which the algorithm is expressed, and the body of pure mathematics needed. All this is developed logically from first prin...

The aim of this work is the development and application of a partial evaluation procedure for rewriting-based functional logic programs. Functional logic programming languages unite the two main declarative programming paradigms. The rewriting-based computational model extends traditional functional programming languages by incorporating logical features, including logical variables and built-in search, into its framework. This work is the first to address the automatic specialisation of these functional logic programs. In particular, a theoretical framework for the partial evaluation of rewriting-based functional logic programs is defined and its correctness is established. Then, an algorithm is formalised which incorporates the theoretical framework for the procedure in a fully automatic technique. Constraint solving is used to represent additional information about the terms encountered during the transformation in order to improve the efficiency and size of the residual programs. ...

The semantics of a hardware description language is usually given informally in terms of how a simulator should behave. We give an operational semantics of simple version of Verilog hardware description language. We also outline some techniques of possible formal reasoning based on the operational semantics.

Most hardware verification techniques tend to fall under one of two broad, yet separate caps: simulation or formal verification. This paper briefly presents a framework in which formal verification plays a crucial role within the standard approach currently used by the hardware industry. As a basis for this, the formal semantics of Verilog HDL are defined, and properties about synchronization and mutual exclusion algorithms are proved.

We formalise the semantics of V \Gamma , a simple version of Verilog hardware description language using an extension of Duration Calculus. The language is simple enough for experimenting formalisation, but contains sufficient features for being practically relevant. V \Gamma programs can exhibit a rich variety of computations, and it is therefore necessary to extend Duration Calculus with several features, including Weakly Monotonic Time, infinite intervals and fixed point operators. The semantics is compositional and can be used as the formal basis of a formal theory of Verilog. Gerardo Schneider is a fellow of UNU/IIST, on leave from Catholic University of Pelotas, Brazil, where he is a lecturer. Xu Qiwen is a Research Fellow of UNU/IIST. His research interest is in Formal Techniques of Programming, including Theory for Concurrency and Real Time, Verification and Design Calculi. E-mail: qxu@iist.unu.edu Copyright c fl 1998 by UNU/IIST, Gerardo Schneider and Xu Qiwen Contents...

This paper presents the derivation of a denotational semantics from an operational semantics for a subset of the widely used hardware description language Verilog. Our aim is to build an equivalence between the operational and denotational semantics. We propose a discrete time semantic model for Verilog.

There are many variants of DC, each of which is designed to deal with a specific feature of real-time computing systems, such as liveness properties, recursive programs, divergence, superdense computation of imperative languages. This report attempts to integrate those variants, and provides a DC-based design method for the mixed software/hardware systems. The language is a conservative extension of DC in the sense that it adopts the same semantic definition for all the ingredients of DC. We add the weak chop inverse, higher order quantification, substitution and point values of state variables into DC, and show that the new language preserves all the laws of variants of DC, including Neighbourhood Logic, Duration Calculus with Iteration, Higherorder Duration Calculus, DC with Super-dense Chop, and Recursive Duration Calculus. The language has been successfully used in formalising an industrial specification language Timed RSL and the Hardware Description Language Verilog. He Jifeng ...

We give an operational semantics of simple version of Verilog hardware description language. Gerardo Schneider is a fellow of UNU/IIST, on leave from Catholic University of Pelotas, Brazil, where he is a lecturer. Xu Qiwen is a Research Fellow of UNU/IIST. His research interest is in Formal Techniques of Programming, including Theory for Concurrency and Real Time, Verification and Design Calculi. E-mail: qxu@iist.unu.edu Copyright c fl 1998 by UNU/IIST, Gerardo Schneider and Xu Qiwen Contents i Contents 1 Introduction 1 2 A Subset of Verilog and its Operational Semantics 1 2.1 Procedural Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.4 Event control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.5 Continuous Assignment . . ....

An operational semantics of a significant subset of the Verilog Hardware Description Language (HDL) is presented. The semantics is encoded using the logic programming language Prolog in a literate programming style. This allows the associated documentation to be maintained in step with the semantics, and the printed version to be presented in a standard mathematical operational semantics style. It also enables the semantics to be directly animated using a Prolog interpreter. Using this approach allows the exploration of sometimes subtle behaviours of parallel programs and the possibility of rapid changes or additions to the semantics of the language covered that could be missed otherwise. In addition, it provides an extra check on the validity of the operational semantics.

This report presents an initial step towards a correct synthesis of Verilog. The synthesis is performed by reducing the source program to a normal form through the application of a small set of algebraic laws and subsequent mapping to the Xilinx Netlist Format. Our synthesis approach eliminates semantic mismatch between the Verilog model and the synthesized netlist.