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A CMOS Area Image Sensor With Pixel Level A/D Conversion
 IN ISSCC DIGEST OF TECHNICAL PAPERS
, 1995
"... A CMOS 64 x 64 pixel area image sensor chip using SigmaDelta modulation at each pixel for A/D conversion is described. The image data output is digital. The chip was fabricated using a 1.2µm two layer metal single layer poly nwell CMOS process. Each pixel block consists of a phototransistor and ..."
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Cited by 34 (7 self)
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A CMOS 64 x 64 pixel area image sensor chip using SigmaDelta modulation at each pixel for A/D conversion is described. The image data output is digital. The chip was fabricated using a 1.2µm two layer metal single layer poly nwell CMOS process. Each pixel block consists of a phototransistor and 22 MOS transistors. Test results demonstrate a dynamic range potentially greater than 93dB, a signal to noise ratio (SNR) of up to 61dB, and dissipation of less than 1mW with a 5V power supply.
On the Stability of Sigma Delta Modulators
 IEEE TRANSACTLONS ON SIGNAL PROCESSING, VOL. 41. NO. 7. JULY 1993
, 1993
"... In this paper we propose a framework for stability analysis of EA modulators, and argue that limit cycles for constant inputs are natural objects to investigate in this context. We present a number of analytical and approximate techniques to aid the stability analysis of the double loop and interpol ..."
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Cited by 26 (2 self)
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In this paper we propose a framework for stability analysis of EA modulators, and argue that limit cycles for constant inputs are natural objects to investigate in this context. We present a number of analytical and approximate techniques to aid the stability analysis of the double loop and interpolative modulators, and use these techniques to propose ways of improved design that explicitly take stability into account.
Adaptive digital correction of analog errors in MASH ADCs. I. Offline and blind online calibration
 IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
, 2000
"... Abstract—Cascaded delta–sigma (MASH) modulators for higher order oversampled analogtodigital conversion rely on precise matching of contributions from different quantizers to cancel lower order quantization noise from intermediate delta–sigma stages. This first part of the paper studies the effect ..."
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Cited by 17 (0 self)
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Abstract—Cascaded delta–sigma (MASH) modulators for higher order oversampled analogtodigital conversion rely on precise matching of contributions from different quantizers to cancel lower order quantization noise from intermediate delta–sigma stages. This first part of the paper studies the effect of analog imperfections in the implementation, such as finite gain of the amplifiers and capacitor ratio mismatch, and presents algorithms and architectures for digital correction of such analog imperfections, as well as gain and spectral distortion in the signal transfer function. Digital correction is implemented by linear finiteimpulse response (FIR) filters, of which the coefficients are determined through adaptive offline or online calibration. Of particular interest is an online “blind ” calibration technique, that uses no reference and operates directly on the digital output during conversion, with the only requirement on the unknown input signal that its spectrum be bandlimited. Behavioral simulations on dualquantization oversampled converters demonstrate nearperfect adaptive correction and significant improvements in signaltoquantizationnoise performance over the uncalibrated case, using as few as 5 FIR coefficients. An alternative online adaptation technique using test signal injection and experimental results from silicon are presented in the second part, in a companion paper [1]. Index Terms—Adaptation, analogtodigital conversion, blind
Reconstruction of oversampled bandlimited signals from sigma delta encoded binary sequences
 IEEE Transactions on Signal Processing
, 1994
"... AbstractWe consider the application of EA modulators to analogtodigital conversion. We have previously shown that for constant input signals, optimal nonlinear decoding can achieve large gains in signaltonoise ratio (SNR) over linear decoding. In this paper we show a similar result for bandlimi ..."
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Cited by 13 (1 self)
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AbstractWe consider the application of EA modulators to analogtodigital conversion. We have previously shown that for constant input signals, optimal nonlinear decoding can achieve large gains in signaltonoise ratio (SNR) over linear decoding. In this paper we show a similar result for bandlimited input signals. The new nonlinear decoding algorithm is based on projections onto convex sets (POCS), and alternates between a timedomain operation and a band limitation to find a signal invariant under both. The timedomain operation results in a quadratic programming problem. The band limitation can be based on singular value decomposition of a certain matrix. We show simulation results for the SNR.performance of a POCSbased decoder and a linear decoder for the single loop, double loop and twostage CA modulators and for a specific fourthorder interpolative modulator. Depending on the modulator and the oversampling ratio, improvements in SNR of up to 1&20 dB can be achieved. I.
Linearity Enhancement of Multibit \Delta\Sigma A/D and D/A Converters Using Data Weighted Averaging
 IEEE Trans. Circuits Syst. II
, 1995
"... A dynamic element matching algorithm, data weighted averaging, is introduced for use in multibit \Delta\Sigma data converters. Using this algorithm, distortion spectra from DAC linearity errors are shaped by firstorder noise shaping, resulting in a dynamic range improvement of 9 dB/octave when DAC ..."
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Cited by 11 (0 self)
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A dynamic element matching algorithm, data weighted averaging, is introduced for use in multibit \Delta\Sigma data converters. Using this algorithm, distortion spectra from DAC linearity errors are shaped by firstorder noise shaping, resulting in a dynamic range improvement of 9 dB/octave when DAC errors dominate. Combining this technique with random dithering eliminates the aliasing of the DAC errors into baseband. Simulations show that with only 1% element matching 110 dB signaltonoise ratio (18 bits) is achieved for a thirdorder 3bit modulator with an oversampling ratio of 128. 1 Introduction Oversampling \Delta\Sigma data converters have displaced traditional converter architectures in audio and instrumentation applications where low frequency, highresolution and high linearity conversion is required [1]. The high resolution obtained from these converters is attributed to the inherent linearity of a singlebit quantizer in the \Delta\Sigma modulator. This high linearity mak...
DeltaSigma Data Conversion in Wireless Transceivers
, 2002
"... Highperformance analogtodigital converters, digitaltoanalog converters, and fractional frequency synthesizers based on deltasigma (16) modulationcollectively referred to as data convertershave contributed significantly to the high level of integration seen in recent commercial wirel ..."
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Cited by 11 (2 self)
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Highperformance analogtodigital converters, digitaltoanalog converters, and fractional frequency synthesizers based on deltasigma (16) modulationcollectively referred to as data convertershave contributed significantly to the high level of integration seen in recent commercial wireless handset transceivers. This paper presents a tutorial on data converters and their uses and implications with respect to wireless transceiver architectures.
Systematic Approach For DiscreteTime To ContinuousTime Transformation Of
"... this paper, we propose a systematic design method for continuoustime SigmaDelta modulators. The transform technique is used to take into account any variation occuring between two sampling instants in the continuoustime DAC feedback signal. The proposed discretetime to continuoustime transfor ..."
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Cited by 9 (8 self)
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this paper, we propose a systematic design method for continuoustime SigmaDelta modulators. The transform technique is used to take into account any variation occuring between two sampling instants in the continuoustime DAC feedback signal. The proposed discretetime to continuoustime transformation method is general and wellsuited to design automation. A fifthorder lowpass as well as a sixth order bandpass modulators with RZ and NRZ feedback signals are given as design examples. I.
Jouanne, “Use of sigmadelta modulation to control emi from switchmode power supplies
 IEEE Trans. Ind. Elect
, 2001
"... Abstract—Conducted electromagnetic interference (EMI) is a major cause of concern in switchmode power supplies (SMPSs) which commonly use standard pulsewidth modulation (PWM). In this paper, Sigma–Delta (61) modulation is proposed as an alternative switching technique to reduce conducted EMI from a ..."
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Cited by 8 (0 self)
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Abstract—Conducted electromagnetic interference (EMI) is a major cause of concern in switchmode power supplies (SMPSs) which commonly use standard pulsewidth modulation (PWM). In this paper, Sigma–Delta (61) modulation is proposed as an alternative switching technique to reduce conducted EMI from an SMPS. The result of using 61 modulation is a spread in the spectrum of the conducted emissions so that large concentrations of power at discrete frequencies are avoided. Experimental timedomain waveforms and spectra of the switching function of firstorder and secondorder 61 modulators are presented to prove the viability of the scheme for EMI mitigation. These modulators are then applied to a dc–dc converter in an offtheshelf computer power supply and experimental results show a reduction of roughly 5–10 dB V in EMI emissions over standard PWM modulators. Index Terms—Electromagnetic compatibility, electomagnetic conducted interference, Sigma–Delta modulation, switchmode
Deterministic Analysis of Oversampled A/D Conversion and Sigma/Delta Modulation, and Decoding Improvements using Consistent Estimates
, 1993
"... Analogtodigital conversion (ADC) which consists in a double discretization of an analog signal in time and in amplitude is increasingly used in modern data acquisition. However, the conversion process always implies some loss of information due to amplitude quantization. Oversampling is the techni ..."
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Cited by 7 (0 self)
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Analogtodigital conversion (ADC) which consists in a double discretization of an analog signal in time and in amplitude is increasingly used in modern data acquisition. However, the conversion process always implies some loss of information due to amplitude quantization. Oversampling is the technique currently used to reduce this loss of accuracy. The error reduction can be performed by lowpass filtering the quantized signal, thus eliminating the high frequency components of the quantization error signal. This is the classical method used to reconstruct the analog signal from its oversampled and quantized version. This reconstruction scheme yields a mean squared error (MSE) inversely proportional to the oversampling ratio R. The fundamental question pursued in this thesis is the following: how much information is available in the oversampled and quantized version of a bandlimited signal for its reconstruction? In order to identify this information, it is essential to go back to the original description of quantization which is typically deterministic. We show that a reconstruction scheme fully takes this information into account
A ThirdOrder CurrentMode ContinuousTime Sigma Delta Modulator
 In Proc. IEEE International Conference on Electronics, Circuits, and Systems
, 1999
"... In this paper, the design procedure for a thirdorder continuoustime \Sigma\Delta modulator with RZ feedback is described. The circuit is realized using continuoustime currentmode integrators and DACs with switchedcurrent sources. A design method to find the minimum biasing current required to ac ..."
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Cited by 7 (3 self)
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In this paper, the design procedure for a thirdorder continuoustime \Sigma\Delta modulator with RZ feedback is described. The circuit is realized using continuoustime currentmode integrators and DACs with switchedcurrent sources. A design method to find the minimum biasing current required to achieve the desired dynamic range is presented. With a sampling frequency of 25:6MHz, the circuit is expected to achieve 84dB of dynamic range for a 100kHz bandwidth input signal. The circuit operates from a power supply of 1:7V and consumes 7:4mW in a 0:35m CMOS process.