A CMOS 64 # 64 pixel area image sensor chip using Sigma-Delta modulation at each pixel for A#D conversion is described. The image data output is digital. The chip was fabricated using a 1.2#mtwo layer metal single layer poly n-well CMOS process. Each pixel block consists of a phototransistor and 22 MOS transistors. Test results demonstrate a dynamic range potentially greater than 93dB, a signal to noise ratio #SNR# of up to 61dB, and dissipation of less than 1mW with a 5V power supply. 1 Boyd Fowler, Abbas El Gamal, and David X. D. Yang 2 Charge-coupled devices #CCD# are at present the most widely used technology for implementing area image sensors. CCD image sensors have their shortcomings, however. They su#er from low yields, they consume too muchpower #3#, and they are plagued with SNR limitations due to the shifting and detection of analog charge packets, and the fact that data is communicated o# chip in analog form. Several alternatives to CCD area image sensors that use st...

A dynamic element matching algorithm, data weighted averaging, is introduced for use in multi-bit \Delta\Sigma data converters. Using this algorithm, distortion spectra from DAC linearity errors are shaped by first-order noise shaping, resulting in a dynamic range improvement of 9 dB/octave when DAC errors dominate. Combining this technique with random dithering eliminates the aliasing of the DAC errors into baseband. Simulations show that with only 1% element matching 110 dB signal-to-noise ratio (18 bits) is achieved for a third-order 3-bit modulator with an oversampling ratio of 128. 1 Introduction Oversampling \Delta\Sigma data converters have displaced traditional converter architectures in audio and instrumentation applications where low frequency, high-resolution and high linearity conversion is required [1]. The high resolution obtained from these converters is attributed to the inherent linearity of a single-bit quantizer in the \Delta\Sigma modulator. This high linearity mak...

In this paper, the design procedure for a thirdorder continuous-time \Sigma\Delta modulator with RZ feedback is described. The circuit is realized using continuous-time current-mode integrators and DACs with switched-current sources. A design method to find the minimum biasing current required to achieve the desired dynamic range is presented. With a sampling frequency of 25:6MHz, the circuit is expected to achieve 84dB of dynamic range for a 100kHz bandwidth input signal. The circuit operates from a power supply of 1:7V and consumes 7:4mW in a 0:35m CMOS process.

Analog-to-digital conversion (ADC) which consists in a double discretization of an analog signal in time and in amplitude is increasingly used in modern data acquisition. However, the conversion process always implies some loss of information due to amplitude quantization. Oversampling is the technique currently used to reduce this loss of accuracy. The error reduction can be performed by lowpass filtering the quantized signal, thus eliminating the high frequency components of the quantization error signal. This is the classical method used to reconstruct the analog signal from its oversampled and quantized version. This reconstruction scheme yields a mean squared error (MSE) inversely proportional to the oversampling ratio R. The fundamental question pursued in this thesis is the following: how much information is available in the oversampled and quantized version of a bandlimited signal for its reconstruction? In order to identify this information, it is essential to go back to the original description of quantization which is typically deterministic. We show that a reconstruction scheme fully takes this information into account

this paper, we propose a systematic design method for continuous-time Sigma-Delta modulators. The -transform technique is used to take into account any variation occuring between two sampling instants in the continuous-time DAC feedback signal. The proposed discretetime to continuous-time transformation method is general and well-suited to design automation. A fifth-order lowpass as well as a sixth order bandpass modulators with RZ and NRZ feedback signals are given as design examples. I.

Abstract—Conducted electromagnetic interference (EMI) is a major cause of concern in switch-mode power supplies (SMPSs) which commonly use standard pulsewidth modulation (PWM). In this paper, Sigma–Delta (61) modulation is proposed as an alternative switching technique to reduce conducted EMI from an SMPS. The result of using 61 modulation is a spread in the spectrum of the conducted emissions so that large concentrations of power at discrete frequencies are avoided. Experimental time-domain waveforms and spectra of the switching function of first-order and second-order 61 modulators are presented to prove the viability of the scheme for EMI mitigation. These modulators are then applied to a dc–dc converter in an off-the-shelf computer power supply and experimental results show a reduction of roughly 5–10 dB V in EMI emissions over standard PWM modulators. Index Terms—Electromagnetic compatibility, electomagnetic conducted interference, Sigma–Delta modulation, switch-mode

A novel application and generalization of sigma--delta (61) modulation has emerged in three-phase power-electronic converters. A conventional modulator with scalar signals and binary quantizer is generalized to a modulator with vector signals and a hexagonal quantizer. Indeed, power-electronic switching states may be thought of as determining the quantizer outputs. The output spectrum is a key performance measure for both communications and power electronics. This paper analytically derives the output spectrum of the hexagonal modulator with a constant input using ergodic theory and Fourier series on the hexagon. The switching rate of the modulator is important for power-electronic design and formulas for the average switching rate are derived for constant and slowly varying sinusoidal inputs. Index Terms---Ergodic, power electronics, quantization, sigma--delta (61) modulation, spectral analysis.

This paper presents an architecture for multi-mode terminals, strictly speaking multi-mode receivers, exploiting IF sampling with Sigma-Delta ADCs. It is shown that Sigma-Delta ADCs are not only an efficient means of digitizing signals but are a nearly perfect fit to the task of analog-to-digital conversion in multi-mode terminals. For further processing the digitized signal, i.e. channel filtering for FDMA systems as well as decorrelation for spread-spectrum systems, a common hardware is presented.

High-performance analog-to-digital converters, digital-to-analog converters, and fractional- frequency synthesizers based on delta--sigma (16) modulation---collectively referred to as data converters---have contributed significantly to the high level of integration seen in recent commercial wireless handset transceivers. This paper presents a tutorial on data converters and their uses and implications with respect to wireless transceiver architectures.

Signal reconstruction in oversampled A/D conversion (ADC) is classically performed by lowpass filtering the quantized signal. This leads to a mean squared error (MSE) inversely proportional to R 2n+1 where R is the oversampling rate and n is the order of the converter. However, while the estimate given by this reconstruction has the same bandwidth as that of the original analog signal, we show that it does not necessarily lead to the same digital sequence when fed into the same A/D converter. Moreover, under some assumptions, we show analytically that an estimate having the same bandwidth and giving the same digital sequence as those of the original signal should yield an MSE with an upper bound inversely proportional to R 2n+2 , instead of R 2n+1 ; that is an improvement of 3 dB per octave of oversampling, regardless of the order of the converter. We propose a structural analysis covering most currently known configurations of oversampled ADC, which enables us to identify sets o...