Abstract — On-focal-plane signal processing for current-mode active pixel sensors (APS), including fixed pattern noise (FPN) suppression and high-resolution analog-to-digital conversion (ADC), is presented. An FPN suppression circuit that removes the offset current variation between pixels by using a combination of an n-type and a p-type current copier cell is described. The FPN suppression circuit exhibits linear transfer characteristics in the input current range from 0 to 30 "A. On-chip ADC is expected to improve imaging system performance and reliability, while reducing system size, weight, and cost. Operation and performance of a current-mode second-order incremental 1-6 A/D converter with column parallel architecture and for highresolution and medium-slow-speed applications is presented. A 12-bit resolution with 61.5 LSB accuracy at the conversion rate of 5.6 kHz was obtained. The LSB corresponds to less than twelve signal charges of current-mode 10-"m pixel APS’s. Based on the experimental results, a brief description of a possible image sensor with the on-chip signal processing is also described. I.

Kohonen maps are self-organizing neural networks that classify and quantify n-dimensional data into a one- or two-dimensional array of neurons [1]-[2]. Most applications of Kohonen maps use simulations on conventional computers, even- tually coupled to hardware accelerators or dedicated neural computers. The small number of different operations involved in the combined learning and classification process makes however the Kohonen model particularly suited to a dedicated VLSI implementation, taking full advantage of the parallelism and speed that can be obtained on the chip. We propose here a fully analog implementation of a one-dimensional Kohonen map, with on-chip learning and refreshment of on-chip analog synaptic weights. The small number of transistors in each cell allows a high degree of parallelism in the operations, what greatly improves the computation speed compared to other implementations. This paper will emphasize on the storage of analog synaptic weights, based on the principle of current copiers; it will be shown that this technique can be used successfully for the realization of VLSI Kohonen maps.

Abstract—An accurate CMOS current source for current-mode low-voltage differential transmitter drivers has been designed and fabricated. It is composed of binary weighted current mirrors with built-in self-calibration circuits. The proposed self-measurement and calibration circuits can calibrate upon the collective effects of different error contributors due to process, power supply, and temperature variations. The design has been fabricated in standard 0.35- m CMOS technology. Measurement results show that the differential output voltage can be self-calibrated to 1 % accuracy with 16 % reference current variation, 60 % power supply variation, or 13 % load resistance variation, respectively. Index Terms—Built-in self-measurement, CMOS integrated circuits, current-mode transmitter driver, low-voltage, self-calibration. I.

A new clock-feedthrough compensation scheme for switchedcurrent circuits is proposed. The scheme is especially suited for the design of delay lines for high-frequency operation. The circuit operates by using an improved two-step technique, in which the input is sampled in a parallel combination of a coarse and a fine memory transistor. Since both transistors are of the same type, large switching transients compared to the conventional SSS 2 III scheme can be avoided. Using the proposed circuit, the coarse memory has considerably more time to settle. Compared to the simple cell, the circuit solution requires only one extra switch and one additional clock phase. Index Terms--- Analog sampled-data circuits, charge injection, sample /hold, switched-current circuits. I. INTRODUCTION A major limitation in switched-current applications is clock feedthrough (CFT), which occurs when a switch transistor is connected to a holding capacitor. CFT is caused by carriers released from the channel...

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In this thesis a new signal processing technique is presented. This technique exploits the use of pulses as the signalling mechanism. This Palmo 1 signalling method applied to signal processing is novel, combining the advantages of both digital and analogue techniques. Pulsed signals are robust, inherently low-power, easily regenerated, and easily distributed across and between chips. The Palmo cells used to perform analogue operations on the pulsed signals are compact, fast, simple and programmable.