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13
New Techniques for Efficient Verification with Implicitly Conjoined BDDs
, 1994
"... In previous work, Hu and Dill identified a common cause of BDDsize blowup in highlevel design verification and proposed the method of implicitly conjoined invariants to address the problem. That work, however, had some limitations: the user had to supply the property being verified as an implicit ..."
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Cited by 26 (9 self)
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In previous work, Hu and Dill identified a common cause of BDDsize blowup in highlevel design verification and proposed the method of implicitly conjoined invariants to address the problem. That work, however, had some limitations: the user had to supply the property being verified as an implicit conjunction of BDDs, the heuristic used to decide which conjunctions to evaluate was rather simple, and the termination test, though fast and effective on a set of examples, was not proven to be always correct. In this work, we address those problems by proposing a new, more sophisticated heuristic to simplify and evaluate lists of implicitly conjoined BDDs and an exact termination test. We demonstrate on examples that these more complex heuristics are reasonably efficient as well as allowing verification of examples that were previously intractable.
Reorda. Using symbolic techniques to find the maximum clique in very large sparse graphs
 In Proc. EDAC
, 1995
"... Abstract * Several problems arising in CAD for VLSI, especially in logic and high level synthesis, are modeled as graphtheoretical problems. In particular, minimization problems often require the knowledge of the cliques in a graph. This paper presents a new approach for finding the maximum clique ..."
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Cited by 3 (0 self)
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Abstract * Several problems arising in CAD for VLSI, especially in logic and high level synthesis, are modeled as graphtheoretical problems. In particular, minimization problems often require the knowledge of the cliques in a graph. This paper presents a new approach for finding the maximum clique in realistic graphs. The algorithm is built around a classical branchandbound, but exploits the efficiency of Binary Decision Diagrams and Symbolic Techniques to avoid explicit enumeration of the search space. The approach is proven to be more efficient than classical algorithms, which suffer from the enumeration problem, as well as than purely symbolic implementations, which suffer from the explosion in the size of BDDs. As a result, we are able to compute the maximum clique without introducing approximations for graphs with billions of vertices and transitions. 1.
An Anytime Algorithm for Generalized Symmetry Detection in ROBDDs
"... Abstract — Detecting symmetries has many applications in logic synthesis that include, amongst other things, technology mapping, deciding equivalence of Boolean functions when the input correspondence is unknown and finding supportreducing bound sets. Mishchenko showed how to efficiently detect sym ..."
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Abstract — Detecting symmetries has many applications in logic synthesis that include, amongst other things, technology mapping, deciding equivalence of Boolean functions when the input correspondence is unknown and finding supportreducing bound sets. Mishchenko showed how to efficiently detect symmetries in ROBDDs without the need for checking equivalence of all cofactor pairs. This work resulted in practical algorithms for detecting classical and generalized symmetries. Both the classical and generalized symmetry detection algorithms are monolithic in the sense that they only return a meaningful answer when they are left to run to completion. In this paper we present anytime algorithms for detecting both classical and generalized symmetries, that output pairs of symmetric variables until a prescribed time bound is exceeded. These anytime algorithms are complete in that given sufficient time they are guaranteed to find all symmetric pairs. Anytime generality is not gained at the expense of efficiency since this approach requires only very modest data structure support and offers unique opportunities for optimization so the resulting algorithms are competitive with their monolithic counterparts.
Formal Verification of the PCI Local Bus: A Step Towards IP Core Based SystemOnChip Design Verification
 Carnegie Mellon University
, 1999
"... We describe a methodology for verifying systemonchip designs. In our methodology, the problem of verifying systemonchip designs is decomposed into three tasks. First, we verify, once and for all, the standard bus interconnecting IP Cores in the system . The next task is to verify the glue logic, ..."
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We describe a methodology for verifying systemonchip designs. In our methodology, the problem of verifying systemonchip designs is decomposed into three tasks. First, we verify, once and for all, the standard bus interconnecting IP Cores in the system . The next task is to verify the glue logic, which connects the IP Cores to the buses. Finally, using the verified bus protocols and the IP core designs, temporal properties about the complete system are deduced. To illustrate our methodology, we verify the PCI Local Bus, a widely used bus protocol in systemonchip designs. We demonstrate various modeling and verification techniques for buses by modeling the PCI Local Bus with the symbolic model checker SMV. We have found two potential bugs in the PCI bus specification that await confirmation of the PCI Special Interest Group(PCISIG).
Boolean function manipulation on a parallel system using BDDs
 In HPCN Europe ’97: of the International Conference and
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Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams 1
"... Quantum information processing technology is in its pioneering stage and no proficient method for synthesizing quantum circuits has been introduced so far. This paper introduces an effective analysis and synthesis framework for quantum logic circuits. The proposed synthesis algorithm and flow can ge ..."
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Quantum information processing technology is in its pioneering stage and no proficient method for synthesizing quantum circuits has been introduced so far. This paper introduces an effective analysis and synthesis framework for quantum logic circuits. The proposed synthesis algorithm and flow can generate a quantum circuit using the most basic quantum operators, i.e., the rotation and controlledrotation primitives. The paper introduces the notion of quantum factored forms and presents a canonical and concise representation of quantum logic circuits in the form of quantum decision diagrams (QDD’s), which are amenable to efficient manipulation and optimization including recursive unitary functional bidecomposition. This paper concludes by presenting the QDDbased algorithm for automatic synthesis of quantum circuits.
A Note on Finding a Maximum Clique in a Graph Using BDDs
"... A new approach for the solution of the maximum clique problem for general undirected graphs was presented in the paper titled “Finding the Maximum Clique in a Graph Using BDDs ”, by F.Corno, P.Prinetto and M.Sonza Reorda, in 1993. The approach is based on computing the characteristic function of all ..."
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A new approach for the solution of the maximum clique problem for general undirected graphs was presented in the paper titled “Finding the Maximum Clique in a Graph Using BDDs ”, by F.Corno, P.Prinetto and M.Sonza Reorda, in 1993. The approach is based on computing the characteristic function of all the completely connected components in the graph, and then finding the maximum cost satisfying assignment of such a function. The novelty of the method is in the use of Binary Decision Diagrams (BDDs) for representing and manipulating characteristic functions. However, we observe that the algorithm stated does not produce the right answer for certain graphs. In this paper we show how to overcome this inadequacy and improve the algorithm. 1
Efficient Synthesis of Quantum Logic Circuits by Rotationbased Quantum Operators and Unitary Functional Bidecomposition
"... Quantum information processing technology is in its pioneering stage and no efficient method for synthesizing quantum circuits has been introduced so far. This paper introduces an efficient analysis and synthesis framework for quantum logic circuits. The proposed synthesis algorithm and flow can gen ..."
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Quantum information processing technology is in its pioneering stage and no efficient method for synthesizing quantum circuits has been introduced so far. This paper introduces an efficient analysis and synthesis framework for quantum logic circuits. The proposed synthesis algorithm and flow can generate a quantum circuit using the most basic quantum operators, i.e., the rotation and controlledrotation primitives. We will introduce the notion of quantum factored forms, and develop a canonical and concise representation of quantum logic circuits in the form of quantum decision diagrams (QDD’s) which are amenable to efficient manipulation and optimization including recursive unitary functional bidecomposition. This representation will produce a rigorous graphbased framework for the analysis and synthesis of quantum logic circuits. Subsequently, an effective QDDbased algorithm will be developed and applied to automatic synthesis of quantum logic circuits. 2.
Cadence Labs Cadence Design Systems, Inc.
"... Abstract — In previous work, Hu and Dill identified a common cause of BDDsize blowup in highlevel design verification and proposed the method of implicitly conjoined invariants to address the problem. That work, however, had some limitations: the user had to supply the property being verified as a ..."
Abstract
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Abstract — In previous work, Hu and Dill identified a common cause of BDDsize blowup in highlevel design verification and proposed the method of implicitly conjoined invariants to address the problem. That work, however, had some limitations: the user had to supply the property being verified as an implicit conjunction of BDDs, the heuristic used to decide which conjunctions to evaluate was rather simple, and the termination test, though fast and effective on a set of examples, was not proven to be always correct. In this work, we address those problems by proposing a new, more sophisticated heuristic to simplify and evaluate lists of implicitly conjoined BDDs and an exact termination test. We demonstrate on examples that these more complex heuristics are reasonably efficient as well as allowing verification of examples that were previously intractable. I.
An Anytime Algorithm for Generalized Symmetry Detection in ROBDDs
"... Abstract — Detecting symmetries has many applications in logic synthesis that include, amongst other things, technology mapping, deciding equivalence of Boolean functions when the input correspondence is unknown and finding supportreducing bound sets. Mishchenko showed how to efficiently detect sym ..."
Abstract
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Abstract — Detecting symmetries has many applications in logic synthesis that include, amongst other things, technology mapping, deciding equivalence of Boolean functions when the input correspondence is unknown and finding supportreducing bound sets. Mishchenko showed how to efficiently detect symmetries in ROBDDs without the need for checking equivalence of all cofactor pairs. This work resulted in practical algorithms for detecting classical and generalized symmetries. Both the classical and generalized symmetry detection algorithms are monolithic in the sense that they only return a meaningful answer when they are left to run to completion. In this paper we present anytime algorithms for detecting both classical and generalized symmetries, that output pairs of symmetric variables until a prescribed time bound is exceeded. These anytime algorithms are complete in that given sufficient time they are guaranteed to find all symmetric pairs. Anytime generality is not gained at the expense of efficiency since this approach requires only very modest data structure support and offers unique opportunities for optimization so the resulting algorithms are competitive with their monolithic counterparts.