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New Techniques for Efficient Verification with Implicitly Conjoined BDDs
, 1994
"... In previous work, Hu and Dill identified a common cause of BDDsize blowup in highlevel design verification and proposed the method of implicitly conjoined invariants to address the problem. That work, however, had some limitations: the user had to supply the property being verified as an implicit ..."
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Cited by 26 (9 self)
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In previous work, Hu and Dill identified a common cause of BDDsize blowup in highlevel design verification and proposed the method of implicitly conjoined invariants to address the problem. That work, however, had some limitations: the user had to supply the property being verified as an implicit conjunction of BDDs, the heuristic used to decide which conjunctions to evaluate was rather simple, and the termination test, though fast and effective on a set of examples, was not proven to be always correct. In this work, we address those problems by proposing a new, more sophisticated heuristic to simplify and evaluate lists of implicitly conjoined BDDs and an exact termination test. We demonstrate on examples that these more complex heuristics are reasonably efficient as well as allowing verification of examples that were previously intractable.
Formal Verification of the PCI Local Bus: A Step Towards IP Core Based SystemOnChip Design Verification
 Carnegie Mellon University
, 1999
"... We describe a methodology for verifying systemonchip designs. In our methodology, the problem of verifying systemonchip designs is decomposed into three tasks. First, we verify, once and for all, the standard bus interconnecting IP Cores in the system . The next task is to verify the glue logic, ..."
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Cited by 2 (0 self)
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We describe a methodology for verifying systemonchip designs. In our methodology, the problem of verifying systemonchip designs is decomposed into three tasks. First, we verify, once and for all, the standard bus interconnecting IP Cores in the system . The next task is to verify the glue logic, which connects the IP Cores to the buses. Finally, using the verified bus protocols and the IP core designs, temporal properties about the complete system are deduced. To illustrate our methodology, we verify the PCI Local Bus, a widely used bus protocol in systemonchip designs. We demonstrate various modeling and verification techniques for buses by modeling the PCI Local Bus with the symbolic model checker SMV. We have found two potential bugs in the PCI bus specification that await confirmation of the PCI Special Interest Group(PCISIG).
An Anytime Algorithm for Generalized Symmetry Detection in ROBDDs
"... Abstract — Detecting symmetries has many applications in logic synthesis that include, amongst other things, technology mapping, deciding equivalence of Boolean functions when the input correspondence is unknown and finding supportreducing bound sets. Mishchenko showed how to efficiently detect sym ..."
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Cited by 2 (0 self)
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Abstract — Detecting symmetries has many applications in logic synthesis that include, amongst other things, technology mapping, deciding equivalence of Boolean functions when the input correspondence is unknown and finding supportreducing bound sets. Mishchenko showed how to efficiently detect symmetries in ROBDDs without the need for checking equivalence of all cofactor pairs. This work resulted in practical algorithms for detecting classical and generalized symmetries. Both the classical and generalized symmetry detection algorithms are monolithic in the sense that they only return a meaningful answer when they are left to run to completion. In this paper we present anytime algorithms for detecting both classical and generalized symmetries, that output pairs of symmetric variables until a prescribed time bound is exceeded. These anytime algorithms are complete in that given sufficient time they are guaranteed to find all symmetric pairs. Anytime generality is not gained at the expense of efficiency since this approach requires only very modest data structure support and offers unique opportunities for optimization so the resulting algorithms are competitive with their monolithic counterparts.
Boolean Function Manipulation on a Parallel System using BDDs
"... This paper describes a distributed algorithm for Boolean function manipulation. The algorithm is based on Binary Decision Diagrams (BDDs), which are one of the most commonly used data structures for representing and manipulating Boolean functions. A new distributed version of a BDD data structure an ..."
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Cited by 1 (0 self)
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This paper describes a distributed algorithm for Boolean function manipulation. The algorithm is based on Binary Decision Diagrams (BDDs), which are one of the most commonly used data structures for representing and manipulating Boolean functions. A new distributed version of a BDD data structure and a distributed implementation of the basic operator for its manipulation are presented. The algorithm is suitable to work on a MIMD architecture and is based on a message passing masterslave paradigm. A package has been written, which uses the PVM library and is portable on different architectures. Two applications have been developed using the parallel BDD package. In both cases the results show that the new distributed version of the algorithm is able to manage BDDs much larger than the ones managed by monoprocessor tools. 1.
Automatic Verification of a Hydroelectric Power Plant
, 1996
"... . We analyze the specification of a hydroelectric power plant by ENEL (the Italian Electric Company). Our goal is to show that for the specification of the plant (its control system in particular) some given properties hold. We were provided with an informal specification of the plant. From suc ..."
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. We analyze the specification of a hydroelectric power plant by ENEL (the Italian Electric Company). Our goal is to show that for the specification of the plant (its control system in particular) some given properties hold. We were provided with an informal specification of the plant. From such informal specification we wrote a formal specification using the CCS/Meije process algebra formalism. We defined properties using  calculus. Automatic verification was carried out using model checking. This was done by translating our process algebra definitions (the model) and calculus formulas into BDDs. In this paper we present the informal specification of the plant, its formal specification, some of the properties we verified and experimental results. 1 Introduction Computer controlled systems are more and more widespread. In safety critical applications this situation calls for formal verification of correctness with respect to the given specifications. Because of the cost ...
Using Symbolic Techniques to find the Maximum Clique in Very Large Sparse Graphs
 In Proc. EDAC
, 1995
"... * Several problems arising in CAD for VLSI, especially in logic and high level synthesis, are modeled as graphtheoretical problems. In particular, minimization problems often require the knowledge of the cliques in a graph. This paper presents a new approach for finding the maximum clique in reali ..."
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* Several problems arising in CAD for VLSI, especially in logic and high level synthesis, are modeled as graphtheoretical problems. In particular, minimization problems often require the knowledge of the cliques in a graph. This paper presents a new approach for finding the maximum clique in realistic graphs. The algorithm is built around a classical branchandbound, but exploits the efficiency of Binary Decision Diagrams and Symbolic Techniques to avoid explicit enumeration of the search space. The approach is proven to be more efficient than classical algorithms, which suffer from the enumeration problem, as well as than purely symbolic implementations, which suffer from the explosion in the size of BDDs. As a result, we are able to compute the maximum clique without introducing approximations for graphs with billions of vertices and transitions. 1. Introduction The importance of efficient algorithms for solving several problems in Graph Theory has been recognized since many yea...
Cadence Labs Cadence Design Systems, Inc.
"... Abstract — In previous work, Hu and Dill identified a common cause of BDDsize blowup in highlevel design verification and proposed the method of implicitly conjoined invariants to address the problem. That work, however, had some limitations: the user had to supply the property being verified as a ..."
Abstract
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Abstract — In previous work, Hu and Dill identified a common cause of BDDsize blowup in highlevel design verification and proposed the method of implicitly conjoined invariants to address the problem. That work, however, had some limitations: the user had to supply the property being verified as an implicit conjunction of BDDs, the heuristic used to decide which conjunctions to evaluate was rather simple, and the termination test, though fast and effective on a set of examples, was not proven to be always correct. In this work, we address those problems by proposing a new, more sophisticated heuristic to simplify and evaluate lists of implicitly conjoined BDDs and an exact termination test. We demonstrate on examples that these more complex heuristics are reasonably efficient as well as allowing verification of examples that were previously intractable. I.