In order to reach the Shannon limit, researchers have found more e#cient error control coding schemes. However, the computational complexity of such error control coding schemes is a barrier to implementing them. Recently, researchers have found that bioinspired analog network decoding is a good approach with better combined power/speed performance than its digital counterparts. However, the lack of CAD (computer aided design) tools makes the analog implementation quite time consuming and error prone. Meanwhile, the performance loss due to the nonidealities of the analog circuits has not been systematically analyzed. Also, how to organize analog circuits so that the nonideal e#ects are minimized has not been discussed.

This panel discusses the following topics. With the ongoing trend towards more and more digitization in applications ranging from multimedia to telecommunications, there is a big debate about whether there will remain a need for analog circuits in scaled technologies. Analog circuits do not seem to take advantage of nanometer CMOS; rather they suffer from it. So if the question is asked “Will analog scale?”, you get conflicting opinions. One camp argues for an almost-all-digital future: analog/RF content should be limited, because it’s difficult, expensive, risky, and can be done with DSP. The opposing camp counters that some critical circuits simply do not want (or need) to scale, and analog is only “risky ” when you let digital designers do it. So, what is the future role of analog circuits in scaled CMOS, and can analog EDA tools help in this? Categories and Subject Descriptors

Behavioral-level performance modeling of analog and mixed-signal systems using support vector machines This paper presents a novel behavioral-level analog and mixedsignal (AMS) system performance modeling methodology using support vector machines (SVM). The method relies on linearly graded sub-spaces to model complex multi-dimensional performance spaces. A detailed evaluation of the method has been carried out for the purpose of potential use for AMS synthesis. The method has been applied to a complex nonideal 2 nd order Sigma-Delta modulator (SDM) and results show good accuracy of performance modeling and numerical efficiency. 1.

We present a new methodology for fast analog circuit synthesis, based on the use of parameterized layout generators and symbolic performance models (SPMs) in the synthesis loop. Fast layout generation is achieved by using efficient parameterized procedural layout generators. Fast performance estimation is achieved by using pre-compiled SPMs, stored as efficient DDD-like structures called Element Coefficient Diagrams. Techniques have been developed to include layout geometry effects in the SPMs. The accuracy and efficiency of the parasitic inclusion technique as well as the proposed methodology have been demonstrated by comparisons to traditional synthesis methods. The proposed methodology is used for the synthesis of opamps and filters and is demonstrated to achieve effective performance closure. 1.

Abstract: This paper presents a method towards hierarchical symbolic analysis of linear analog circuits using twoport networks. The important difference to the ordinary flat symbolic analysis is, that we treat the transistor pairs as blocks and then derive the transfer function with network analyzer without to setup and solve a complicated DAE system for a whole analog circuit. The hierarchical idea can be even used to large circuits in divide and conquer manner. Experimental results obtained with some applications of this method are presented. Key–Words: Symbolic analysis, Two-port network 1

The systematic design of a high-speed, high-accuracy Nyquistrate A/D converter is proposed. The presented design methodology covers the complete flow and is supported by software tools. A generic behavioral model is used to explore the A/D converter's specifications during high-level design and exploration. The inputs to the flow are the specifications of the A/D converter and the technology process. The result is a generated layout and the corresponding extracted behavioral model. The approach has been applied to a real-life test case, where a Nyquist-rate 8-bit 200 MS/s 4-2 interpolating/averaging A/D converter was developed for a WLAN application.

The ever increasing pace of analog IC design demands efficient means of automated design and optimization. Especially important is robust design. Its goal is to produce circuits whose behaviour stays within some predefined range when the manufacturing process variations and environmental effects remain bounded. Most of the design process is still handled by IC designers manually. We present a simple mathematical formulation of the robust design and optimization problem and its transformation into a constrained optimization problem by means of penalty functions. We illustrate the method on a robust differential amplifier design problem. The resulting circuits show that a computer not only can improve circuits designed by humans, but is also capable of designing a circuit with very little initial knowledge. Optimization runs resulted in circuits with similar or even better performance when compared to humanly designed circuits. The method can take advantage of parallel processing, but is still efficient enough to be run on a single computer.

In this paper, a method for nominal design of analog integrated circuits is presented that includes process variations and operating ranges by worst-case parameter sets. These sets are calculated adaptively during the sizing process based on sensitivity analyses. The method leads to robust designs with high parametric yield, while being much more efficient than design centering methods.

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This special session adresses the problems that designers face when implementing analog and digital circuits in nanometer technologies. An introductory embedded tutorial will give an overview of the design problems at hand: the leakage power and process variability and their implications for digital circuits and memories, and the reducing supply voltages, the design productivity and signal integrity problems for embedded analog block s. Next, a panel of experts from both industrial semiconductor houses and design companies, EDA vendors and research institutes will present and discuss with the audience their opinions on whether the design road ends at marker “65nm” or not.