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Boolean analysis of MOS circuits
 IEEE Transactions on Computeraided Design
, 1987
"... The switchlevel model represents a digital metaloxide semiconductor (MOS) circuit as a network of charge storage nodes connected by resistive transistor switches. The functionality of such a network can be expressed as a series of systems of Boolean equations. Solving these equations symbolically ..."
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Cited by 63 (14 self)
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The switchlevel model represents a digital metaloxide semiconductor (MOS) circuit as a network of charge storage nodes connected by resistive transistor switches. The functionality of such a network can be expressed as a series of systems of Boolean equations. Solving these equations symbolically yields a set of Boolean formulas that describe the mapping from input and current state to the new network state. This analysis supports the same class of networks as the switchlevel simulator MOSSIM II and provides the same functionality, including the handling of bidirectional e ects and indeterminate (X) logic values. In the worst case, the analysis of an n node network can yield a set of formulas containing a total of O(n 3) operations. However, all but a limited set of dense, passtransistor networks give formulas with O(n) total operations. The analysis can serve as the basis of e cient programs for a variety oflogic design tasks, including: logic simulation (on both conventional and special purpose computers), fault simulation, test generation, and symbolic veri cation.
COSMOS: A compiled simulator for MOS circuits
 PROCEEDINGS OF THE 24TH DESIGN AUTOMATION CONFERENCE
, 1987
"... The cosmos simulator provides fast and accurate switchlevel modeling of mos digital circuits. It attains high performance by preprocessing the transistor network into a functionally equivalent Boolean representation. This description, produced by the symbolic analyzer anamos, captures all aspects o ..."
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Cited by 52 (0 self)
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The cosmos simulator provides fast and accurate switchlevel modeling of mos digital circuits. It attains high performance by preprocessing the transistor network into a functionally equivalent Boolean representation. This description, produced by the symbolic analyzer anamos, captures all aspects of switchlevel networks including bidirectional transistors, stored charge, different signal strengths, and indeterminate (X) logic values. The lgcc program translates the Boolean representation into a set of machine language evaluation procedures and initialized data structures. These procedures and data structures are compiled along with code implementing the simulation kernel and user interface to produce the simulation program. The simulation program runs an order of magnitude faster than our previous simulator mossim ii.
Algorithmic Aspects of Symbolic Switch Network Analysis
 IEEE Trans. CAD/IC
, 1987
"... A network of switches controlled by Boolean variables can be represented as a system of Boolean equations. The solution of this system gives a symbolic description of the conducting paths in the network. Gaussian elimination provides an efficient technique for solving sparse systems of Boolean eq ..."
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Cited by 16 (5 self)
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A network of switches controlled by Boolean variables can be represented as a system of Boolean equations. The solution of this system gives a symbolic description of the conducting paths in the network. Gaussian elimination provides an efficient technique for solving sparse systems of Boolean equations. For the class of networks that arise when analyzing digital metaloxide semiconductor (MOS) circuits, a simple pivot selection rule guarantees that most s switch networks encountered in practice can be solved with O(s) operations. When represented by a directed acyclic graph, the set of Boolean formulas generated by the analysis has total size bounded by the number of operations required by the Gaussian elimination. This paper presents the mathematical basis for systems of Boolean equations, their solution by Gaussian elimination, and data structures and algorithms for representing and manipulating Boolean formulas.
Symbolic Functional and Timing Verification of TransistorLevel Circuits
 ACM/IEEE INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN
, 1999
"... We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaustively verify a mediumsized modern logic block. Static analysis can handle much larger circuits but is not robust with re ..."
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Cited by 5 (2 self)
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We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaustively verify a mediumsized modern logic block. Static analysis can handle much larger circuits but is not robust with respect to variations from standard circuit structures. Our approach applies symbolic simulation to analyze a circuit over all input combinations without these limitations. We present a prototype simulator (SirSim) and experimental results. We also discuss using SirSim to verify an industrial design which previously required a specialpurpose verification methodology.
Symbolic Timing Simulation Using Cluster Scheduling
, 2000
"... We recently introduced symbolic timing simulation (STS) using datadependent delays as a tool for verifying the timing of fullcustom transistorlevel circuit designs, and for the functional verification of delaydependent logic. While STS leverages efficient symbolic encodings to yield huge gains ov ..."
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We recently introduced symbolic timing simulation (STS) using datadependent delays as a tool for verifying the timing of fullcustom transistorlevel circuit designs, and for the functional verification of delaydependent logic. While STS leverages efficient symbolic encodings to yield huge gains over conventional simulation methodologies, it still suffers from a problem known as event multiplication. We discuss this problem and present an eventlist management technique based on eventclusters, and a new simulator which utilizes this technique. Finally, we demonstrate substantial speedups on a wide range of test cases, including exponential improvement on a simple logic chain.