The introduction of simulation-based analog synthesis tools creates a new challenge for analog modeling. These tools routinely visit 103 to 105 fully simulated circuit solution candidates. What might we do with all this circuit data? We show how to adapt recent ideas from large-scale data mining to build models that capture significant regions of this visited performance space, parametefized by variables manipulated by synthesis, trained by the data points visited during synthesis. Experimental restfits show that we can automatically build useful nonlinear regression models for large analog design spaces.

In this paper we propose a RObust Analog Design tool (ROAD) for post-tuning analog/RF circuits. Starting from an initial design derived from hand analysis or analog circuit synthesis based on simplified models, ROAD extracts accurate posynomial performance models via transistor-level simulation and optimizes the circuit by geometric programming. Importantly, ROAD sets up all design constraints to include large-scale process variations to facilitate the tradeoff between yield and performance. A novel convex formulation of the robust design problem is utilized to improve the optimization efficiency and to produce a solution that is superior to other local tuning methods. In addition, a novel projection-based approach for posynomial fitting is used to facilitate scaling to large problem sizes. A new implicit power iteration algorithm is proposed to find the optimal projection space and extract the posynomial coefficients with robust convergence. The efficacy of ROAD is demonstrated on several circuit examples. 1.

This paper presents an new direct--fitting method to generate posynomial response surface models with arbitrary constant exponents for linear and nonlinear performance parameters of analog integrated circuits. Posynomial models enable the use of efficient geometric programming techniques for circuit sizing and optimization. The automatic generation avoids the time--consuming nature and inaccuracies of handcrafted analytic model generation. The technique is based on the fitting of posynomial model templates to numerical data from SPICE simulations. Attention is paid to estimating the relative `goodness--of--fit' of the generated models. Experimental results illustrate the significantly better accuracy of the new approach.

Many approaches to analog performance parameter macro modeling have been investigated by the research community. These models are typically derived from discrete data obtained from circuit simulation using numerous input combinations of component sizes for a given circuit topology. The simulations are computationally intensive, therefore it is advantageous to reduce the number of simulations necessary to build an accurate macro model. We present a new algorithm for adaptively sampling multi-dimensional black box functions based on Duchon pseudo-cubic splines. The splines readily and accurately model high dimensional functions based on discrete unstructured data and require no tuning of parameters as seen in many other interpolation methods. The adaptive sampler, in conjunction with pseudo-cubic splines, is used to accurately model various analog performance parameters for an operational amplifier topology using fewer sample points than traditional gridded and quasi-random sampling methodologies.

This paper presents a novel method to automatically generate symbolic expressions for both linear and nonlinear circuit characteristics using a template-based fitting of numerical, simulated data. The aim of the method is to generate convex, interpretable expressions. The posynomiality of the generated expressions enables the use of efficient geometric programming techniques when using these expressions for circuit sizing and optimization. Attention is paid to estimating the relative `goodness-of-fit' of the generated expressions. Experimental results illustrate the capabilities of the approach.

Pólya proved that if a real, homogeneous polynomial is positive on the nonnegative orthant (except at the origin), then it is the quotient of two homogeneous polynomials with no negative coefficients. We generalize this from polynomials to signomials with arbitrary rational exponents; we also show that Pólya’s theorem does not generalize to arbitrary signomials (i.e., with irrational (real) exponents). 1

Semiconductor manufacturing process variations are worsening with continued reduction in transistor feature sizes. However, technology scaling is the engine driving the semiconductor industry and must continue. When variations worsen to the point that they can no longer be addressed solely at the device and circuit levels, the next logical step is to develop variation-tolerant microarchitectures. This thesis presents research on modeling, characterizing, and mitigating the impact of process variations on the energy-efficiency of modern chip-multiprocessors. New models are developed for how variations impact chip-multiprocessor power and performance at a variety of granularities, from within a single core to among dies in a speed bin. These numerical models, fit to HSPICE data, achieve orders of magnitude lower error than the analytical models traditionally used in microarchitecture-level research. These models are used to drive the motivation and evaluation of two new schemes for reclaiming some of the energy-efficiency that is lost to process variations, both predicated on addressing variation in static power. Variation-aware level selection (VALS) works in the context of dynamic voltage/frequency scaling (DVFS), a popular method for improving energy-efficiency. In fine-grained

Body biasing has been demonstrated to be effective in addressing process variability in a variety of simple chip designs. However, for modern microprocessor ICs with multiple cores and dynamic voltage/frequency scaling (DVFS), the use of body biasing has significant implications. For a 16core chip-multiprocessor implemented in a high-performance 22 nm technology, the body biases required to meet the frequency target at the lowest and highest voltage/frequency levels differ by an average of 0.7 V, implying that per-level biases are required to fully leverage body biasing. The need to make abrupt changes in the body biases when the voltage/frequency level changes affects the cost/benefit analysis of body biasing schemes. It is demonstrated that computing unique body biases for each voltage/frequency level at chip power-on offers the best tradeoff among a variety of methods in terms of area, performance, and power. While continuously adjusting the body biases during operation offers improvements in energy/efficiency, these benefits were outweighed by the implementation costs. The implementation costs of continuously adjusting the body biases are dominated by the settling time of the controller. Existing controllers designed for simple general-purpose microprocessors do not optimize for settling time, and require D/A converters with high time constants. We propose a