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Computeraided design of analog and mixedsignal integrated circuits
 PROCEEDINGS OF THE IEEE
, 2000
"... This survey presents an overview of recent advances in the state of the art for computeraided design (CAD) tools for analog and mixedsignal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixedsignal ICs and emerging systemsonachip (SoC) ..."
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Cited by 81 (13 self)
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This survey presents an overview of recent advances in the state of the art for computeraided design (CAD) tools for analog and mixedsignal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixedsignal ICs and emerging systemsonachip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuousvalued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved.
Remembrance of Circuits Past : Macromodeling by Data Mining in Large Analog Design Spaces
 in Proceedings of DAC
, 2002
"... The introduction of simulationbased analog synthesis tools creates a new challenge for analog modeling. These tools routinely visit 103 to 105 fully simulated circuit solution candidates. What might we do with all this circuit data? We show how to adapt recent ideas from largescale data mining to ..."
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Cited by 38 (0 self)
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The introduction of simulationbased analog synthesis tools creates a new challenge for analog modeling. These tools routinely visit 103 to 105 fully simulated circuit solution candidates. What might we do with all this circuit data? We show how to adapt recent ideas from largescale data mining to build models that capture significant regions of this visited performance space, parametefized by variables manipulated by synthesis, trained by the data points visited during synthesis. Experimental restfits show that we can automatically build useful nonlinear regression models for large analog design spaces.
Support Vector Machines for Analog Circuit Performance Representation
 in Proceedings of DAC
, 2003
"... The use of Support Vector Machines (SVMs) to represent the performance space of analog circuits is explored. In abstract terms, an analog circuit maps a set of input design parameters to a set of performance figures. This function is usually evaluated through simulations and its range defines the fe ..."
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Cited by 25 (6 self)
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The use of Support Vector Machines (SVMs) to represent the performance space of analog circuits is explored. In abstract terms, an analog circuit maps a set of input design parameters to a set of performance figures. This function is usually evaluated through simulations and its range defines the feasible performance space of the circuit. In this paper, we directly model performance spaces as mathematical relations. We study approximation approaches based on twoclass and oneclass SVMs, the latter providing a better tradeoff between accuracy and complexity avoiding "curse of dimensionality" issues with 2class SVMs. We propose two improvements of the basic oneclass SVM performances: conformal mapping and active learning. Finally we develop an efficient algorithm to compute projections, so that topdown methodologies can be easily supported.
Performance tradeoff analysis of analog circuit by normal boundary intersection
 In DAC
, 2003
"... We present a new technique to examine the tradeoff regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on circuit simulation, sizing rules, which capture elementary topological and technological constraints, and an advanced multic ..."
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Cited by 20 (2 self)
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We present a new technique to examine the tradeoff regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on circuit simulation, sizing rules, which capture elementary topological and technological constraints, and an advanced multicriteria optimization formulation called normalboundary intersection. We are able to efficiently calculate a wellbalanced discretization of a Pareto surface, identify the active constraints, which prevent a further improvement, and even rank these constraints in terms of stringency. Experimental results demonstrate the efficacy and efficiency of the method and its potential for topology selection and analog synthesis.
Performance modeling of analog integrated circuits using leastsquares support vector machines
 in Proc. Des. Autom. and Test Europe Conf
"... This paper describes the application of LeastSquares Support Vector Machine (LSSVM) training to analog circuit performance modeling as needed for accelerated or hierarchical analog circuit synthesis. The training is a type of regression, where a function of a special form is fit to experimental ..."
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Cited by 18 (1 self)
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This paper describes the application of LeastSquares Support Vector Machine (LSSVM) training to analog circuit performance modeling as needed for accelerated or hierarchical analog circuit synthesis. The training is a type of regression, where a function of a special form is fit to experimental performance data derived from analog circuit simulations. The method is contrasted with a feasibility model approach based on the more traditional use of SVMs, namely classification. A Design of Experiments (DOE) strategy is reviewed which forms the basis of an efficient simulation sampling scheme. The results of our functional regression are then compared to two other DOEbased fitting schemes: a simple linear leastsquares regression and a regression using posynomial models. The LSSVM fitting has advantages over these approaches in terms of accuracy of fit to measured data, prediction of intermediate data points and reduction of free model tuning parameters. 1.
Generation of yieldaware Pareto surfaces for hierarchical circuit design space exploration
 in Proc. Des. Autom. Conf., 2006
"... Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a nondominated sorting based global optimization algorithm to generate the nominal pareto front efficiently using a simulatorinaloop approach. Th ..."
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Cited by 15 (1 self)
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Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a nondominated sorting based global optimization algorithm to generate the nominal pareto front efficiently using a simulatorinaloop approach. The solutions on this pareto front combined with efficient Monte Carlo approximation ideas are then used to compute the yieldaware pareto fronts. We show experimental results for both the nominal and yieldaware pareto fronts for power and phase noise for a voltage controlled oscillator (VCO) circuit. The presented methodology computes yieldaware pareto fronts in approximately 56 times the time required for a single circuit synthesis run and is thus practically efficient. We also show applications of yieldaware paretos to find the optimal VCO circuit to meet the system level specifications of a phase locked loop.
Analog performance space exploration by FourierMotzkin elimination with application to hierarchical sizing
 in Proc. of ICCAD
, 2004
"... Analog performance space exploration identifies the range of feasible performance values of a given circuit topology. It is an extremely challenging task of great importance to topology selection and hierarchical sizing. In this paper, a novel technique for the efficient simulationbased exploration ..."
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Cited by 8 (1 self)
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Analog performance space exploration identifies the range of feasible performance values of a given circuit topology. It is an extremely challenging task of great importance to topology selection and hierarchical sizing. In this paper, a novel technique for the efficient simulationbased exploration of highdimensional performance spaces is presented. To this end, fundamental circuit design knowledge is described by constraint functions. Based on a linearization of the latter and of the circuit performance functions, a description of the feasible performance range in the form of a polytope is derived. Moreover, the approach is integrated into a hierarchical sizing method, where it propagates topological and technological constraints bottomup. Practical application results demonstrate the efficiency and usefulness of the new method. 1.
Hierarchical Constraint Transformation using Directed Interval Search for Analog System Synthesis
, 1999
"... In this paper, we present a hierarchical approach for constraint transformation. The important features of this are: a genetic algorithm (GA) based search engine that computes design parameter ranges, a hierarchically organized characterization mechanism based on the concept of directed intervals th ..."
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Cited by 6 (4 self)
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In this paper, we present a hierarchical approach for constraint transformation. The important features of this are: a genetic algorithm (GA) based search engine that computes design parameter ranges, a hierarchically organized characterization mechanism based on the concept of directed intervals that assists the search engine and an analog performance estimator. Experiments were conducted comparing the hierarchical approach with a flat bottomup one. The results obtained demonstrate the effectiveness of the former approach. Experimental results highlighting the impact of using the characterization information within the constraint transformation process are also presented. 1. Introduction and Motivation Crucial to a topdown mixedsignal design process [12] is a mechanism to propagate the specifications and constraints on the design elements used at one level to those at the next level. This task of transforming the systemlevel specifications onto component level constraints is c...
Behavioral modeling for analog systemlevel simulation by wavelet collocation method
 IEEE Trans. Circuits Syst. II
, 2003
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ACTIF: a highlevel power estimation tool for Analog ContinuousTime Filters
 Proc ICCAD2000
, 2000
"... A tool is presented that gives a highlevel estimation of the power consumed by an analog continuoustime OTAC filter when given only highlevel input parameters such as dynamic range and signal swing. When used in combination with estimators for other building blocks (ADC’s, DAC’s, mixers,…) a tru ..."
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Cited by 2 (1 self)
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A tool is presented that gives a highlevel estimation of the power consumed by an analog continuoustime OTAC filter when given only highlevel input parameters such as dynamic range and signal swing. When used in combination with estimators for other building blocks (ADC’s, DAC’s, mixers,…) a truly highlevel analog system exploration becomes feasible such as needed for architectural exploration of telecom systems. In literature only fundamental relations exist for analog filters, that predict the power with an error of orders of magnitude, which makes them hard to use in real system design. ACTIF combines existing filter synthesis methods with new behavioral models for transconductance stages in a novel way to obtain an optimized highlevel yet accurate power estimation. To verify the presented approach, two recently published design examples are compared with the results from ACTIF. 1.