The introduction of simulation-based analog synthesis tools creates a new challenge for analog modeling. These tools routinely visit 103 to 105 fully simulated circuit solution candidates. What might we do with all this circuit data? We show how to adapt recent ideas from large-scale data mining to build models that capture significant regions of this visited performance space, parametefized by variables manipulated by synthesis, trained by the data points visited during synthesis. Experimental restfits show that we can automatically build useful nonlinear regression models for large analog design spaces.

In this paper, we present a new approach for realistic worst-case analysis of VLSI circuit performances and a novel methodology for circuit performance optimization. Circuit performance measures are modeled as response surfaces of the designable and uncontrollable (noise) parameters. Worst-case analysis proceeds by first computing the worst-case circuit performance value and then determining the worst-case noise parameter values by solving a nonlinear programming problem. A new circuit optimization technique is developed to find an optimal design point at which all of the circuit specifications are met under worst-case conditions. This worst-case design optimization method is formulated as a constrained multi-criteria optimization. The methodologies described in this paper are applied to several VLSI circuits to demonstrate their accuracy and efficiency. Keywords Worst-case analysis, worst-case design optimization. I. Introduction I NEVITABLE fluctuations in the manufacturing proces...

Introduction As the number, and diversity, of computer aided design tools used by VLSI circuit designers continues to grow, the need for CAD frameworks increases. While a precise definition of a CAD framework is difficult to give, it is convenient to view a CAD framework as a collection of underlying facilities and services that support activities performed by CAD tool developers, CAD system integrators, and CAD tool users [7]. In general these services include CAD tool integration, design data management, design process management, and design methodology management. Carnegie Mellon's interest in VLSI CAD frameworks began more than seven years ago. Whereas most of the early VLSI design systems that were being developed at that time were closed design environments, constructed to work with a fixed design methodology and a customized suite of CAD tools and design representations, our program was more general in nature. Our initial efforts, which resulted in the Ulysses[1] and Ca

Abstract—A model for process-induced parameter variations is proposed, combining die-to-die, within-die systematic, and withindie random variations. This model is put to use toward finding suitable timing margins and device file settings, to verify whether a circuit meets a desired timing yield. While this parameter model is cognizant of within-die correlations, it does not require specific variation models, layout information, or prior knowledge of intrachip covariance trends. The approach works with a “generic ” critical path, leading to what is referred to as a “processspecific” statistical-timing-analysis technique that depends only on the process technology, transistor parameters, and circuit style. A key feature is that the variation model can be easily built from process data. The derived results are “full-chip, ” applicable with ease to circuits with millions of components. As such, this provides a way to do a statistical timing analysis without the need for detailed statistical analysis of every path in the design. Index Terms—Correlations, die-to-die variations, generic critical path, parametric yield, principal component analysis, statistical timing analysis, timing margin, virtual corner, within-die variations. I.

In this report a method for the design centering of analog circuits, based on worstcase distances (WCD) is presented. In order to keep the linearization error small, only the WCDs and not the strongly nonlinear objective function itself is linearized. For the resulting nonlinear trust-region problem the generalized boundary curve (GBC) is derived as a method to determine a solution with a good ratio between error reduction and norm of the parameter correction. This parameter correction is used in a standard iterative trust-region optimization algorithm. Results calculated on a circuit example show a signifcant reduction of iterations compared to a standard gradient-based optimization algorithm. Thus, design centering becomes applicable within industrial analog circuit design.

This paper presents a methodology for concurrently optimizing an IC fabrication process and a standard cell library in order to maximize overall yield. The approach uses the Concurrent Subspace Optimization (CSSO) algorithm, which has been developed for general coupled, multidisciplinary optimization problems. An example is provided showing the application of the algorithm to optimizing a mixed analog-digital library on a CMOS process. 1 Introduction In order to develop high-performance, integrated systems, IC designers are reliant upon having highperformance cell libraries. The development, characterization, and optimization of cell libraries is itself a very complex task, requiring the coordinated efforts of circuit designers and fabrication process engineers. While circuit designers may optimize the performance of individual cells by adjusting device geometries, they do so under the constraints of a fixed fabrication process. One of the key responsibilities of the fabrication proce...

Process and environmental variations continue to present significant challenges to designers of high-performance integrated circuits. In the past few years, while much research has been aimed at handling parameter variations as part of timing analysis, few proposals have actually included ways to interpret the results of this parameterized static timing analysis (PSTA) step. In this paper, we propose a new post-variational analysis metric that canbeusedtoquantifytherobustness of designs to parameter variations. In addition to helping designers diagnose if and when different nodes can fail, this metric can give insights on what to fix, by identifying nodes with small robustness values and proceeding to fix those nodes first. Inspired by the rich literature on design centering, tolerancing, and tuning (DCTT), we use distance as a measure for robustness. Our analysis thus determines the minimum distance from the nominal point in the parameter space to any timing violation, and works under the assumption that parameters are specified as ranges rather than statistical distributions. We demonstrate the usefulness of this distance-based robustness metric on circuit blocks extracted from a commercial 45nm microprocessor. 1.