Introduction Deterministic computer simulations of physical phenomena are becoming widely used in science and engineering. Computers are used to describe the flow of air over an airplane wing, combustion of gasses in a flame, behavior of a metal structure under stress, safety of a nuclear reactor, and so on. Some of the most widely used computer models, and the ones that lead us to work in this area, arise in the design of the semiconductors used in the computers themselves. A process simulator starts with a data structure representing an unprocessed piece of silicon and simulates the steps such as oxidation, etching and ion injection that produce a semiconductor device such as a transistor. A device simulator takes a description of such a device and simulates the flow of current through it under varying conditions to determine properties of the device such as its switching speed and the critical voltage at which it switches. A circuit simulator takes a list of devices and the

The introduction of simulation-based analog synthesis tools creates a new challenge for analog modeling. These tools routinely visit 103 to 105 fully simulated circuit solution candidates. What might we do with all this circuit data? We show how to adapt recent ideas from large-scale data mining to build models that capture significant regions of this visited performance space, parametefized by variables manipulated by synthesis, trained by the data points visited during synthesis. Experimental restfits show that we can automatically build useful nonlinear regression models for large analog design spaces.

Hierarchy plays a significant role in the design of digital and analog circuits. At each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. This paper proposes a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. A vertical binary search technique is used to generate the feasibility macromodel and a layered volume-slicing methodology with radial basis functions is used to generate the performance macromodel. Macromodels have been developed and verified for both analog and digital blocks. Analog macromodels have been developed at three different levels of hierarchy (current mirror, opamp, and A/D converter). The impact of different fabrication processes on the performance of analog circuits have also been explored. Though the modeling technique has been fine tuned to handle analog circuits the approach is ...

Abstract—Under manufacturing process variation, a path through a net is called longest if there exists a process condition under which the path has the maximum delay among all paths through the net. There are often multiple longest paths for each net, due to different process conditions. In addition, a local defect, such as resistive open or a resistive bridge, increases the delay of the affected net. To detect delay faults due to local defects and process variation, it is necessary to test all longest paths through each net. Previous approaches to this problem were inefficient because of the large number of paths that are not longest. This paper presents an efficient method to generate the set of longest paths for delay test under process variation. To capture both structural and process correlation between path delays, we use linear delay functions to express path delays under process variation. A novel technique is proposed to prune paths that are not longest, resulting in a significant reduction in the number of paths. In experiments on ISCAS circuits, our number of longest paths is 1 % to 6 % of the previous best approach, with 300X less running time.

When designing large complex vessels, the evaluation of a particular design can be both complicated and time consuming. Designers often resort to the use of concept design models enabling both a reduction in complexity and time for evaluation. Various optimisation methods are then typically used to explore the design space facilitating the selection of optimum or near optimum designs. It is now possible to incorporate considerations of seakeeping, stability and costs at the earliest stage in the ship design process. However, to ensure that reliable results are obtained, the models used are generally complex and computationally expensive. Methods have been developed which avoid the necessity to carry out an exhaustive search of the complete design space. One such method is described which is concerned with the application of the theory of Design Of Experiments (DOE) enabling the design space to be efficiently explored. The objective of the DOE stage is to produce response surfaces which can then be used by an optimisation module to search the design space. It is assumed that the concept exploration tool whilst being a simplification of the design problem, is still sufficiently complicated to enable reliable evaluations of a particular design concept. The response surface is used as a representation of the concept exploration tool, and by it’s nature can be used to rapidly evaluate a design concept hence reducing

In order to design high performance circuits, the relationship between circuit perfor- mance and design parameters must be precisely established. Previously, experimental design techniques have been employed for performance modeling of MOS VLSI devices and circuits. In this paper we describe a new computer-aided methodology for charac- terizing a family of electrical circuits. This methodology is based on multi-stage experi- mental design and prediction through data interpolation. The technique presented here is fully automated and hence helps the designer in efficiently characterizing any circuit response based on full circuit simulations. Through examples, we show the power of this technique in characterizing highly non-linear relationships between circuit performance and the design parameters, in a variety of applications.