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Performance optimization of VLSI interconnect layout
 Integration, the VLSI Journal
, 1996
"... This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. ..."
Abstract

Cited by 103 (32 self)
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This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, nontree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.
Clock Distribution Networks in Synchronous Digital Integrated Circuits
 Proc. IEEE
, 2001
"... this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path ..."
Abstract

Cited by 56 (5 self)
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this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path and the clock skew of that path are described in Section IV. The interplay among the aforementioned three subsystems making up a synchronous digital system is described in Section V; particularly, how the timing characteristics of the memory and logic elements constrain the design and synthesis of clock distribution networks. Different forms of clock distribution networks, such as buffered trees and Htrees, are discussed. The automated layout and synthesis of clock distribution networks are described in Section VI. Techniques for making clock distribution networks less sensitive to process parameter variations are discussed in Section VII. Localized scheduling of the clock delays is useful in optimizing the performance of highspeed synchronous circuits. The process for determining the optimal timing characteristics of a clock distribution network is reviewed in Section VIII. The application of clock distribution networks to highspeed circuits has existed for many years. The design of the clock distribution network of certain important VLSIbased systems has been described in the literature, and some examples of these circuits are described in Section IX. In an effort to provide some insight into future and evolving areas of research relevant to highperformance clock distribution networks, some potentially important topics for future research are discussed in Section X. Finally, a summary of this paper with some concluding remarks is provided in Section XI
Modeling and Optimization of VLSI Interconnects
, 1999
"... As very large scale integrated (VLSI) circuits move into the era of deepsubmicron (DSM) technology and gigahertz frequency, the system performance has increasingly become dominated by the interconnect delay. This dissertation presents five related research topics on interconnect layout optimizati ..."
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Cited by 5 (0 self)
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As very large scale integrated (VLSI) circuits move into the era of deepsubmicron (DSM) technology and gigahertz frequency, the system performance has increasingly become dominated by the interconnect delay. This dissertation presents five related research topics on interconnect layout optimization, and interconnect extraction and modeling: the multisource wire sizing (MSWS) problem, the simultaneous transistor and interconnect sizing (STIS) problem, the global interconnect sizing and spacing (GISS) problem, the interconnect capacitance extraction problem, and the interconnect inductance extraction problems. Given a routing tree with multiple sources, the MSWS problem determines the optimal widths of the wire segments such that the delay is minimized. We reveal several interesting properties for the optimal MSWS solution, of which the most important is the bundled refinement property. Based on this property, we propose a polynomial time algorithm, which uses iterative bundled refinement operations to compute lower and upper bounds of an optimal solution. Since the algorithm often achieves identical lower and upper bounds in experiments, the optimal solution is obtained simply by the bound computation. Furthermore, this algorithm can be used for singlesource wire sizing problem and runs 100x xxi faster than previous methods. It has replaced previous singlesource wire sizing methods in practice.
Sakallah, “Optimization of critical paths in circuits withlevelsensitive latches
 in Proc. Int. Conf. ComputerAided Design
, 1994
"... A simple extension of the critical path method is presented which allows more accurate optimization of circuits with levelsensitive latches. The extended formulation provides a sufficient set of constraints to ensure that, when all slacks are nonnegative, the corresponding circuit will be free of ..."
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Cited by 1 (0 self)
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A simple extension of the critical path method is presented which allows more accurate optimization of circuits with levelsensitive latches. The extended formulation provides a sufficient set of constraints to ensure that, when all slacks are nonnegative, the corresponding circuit will be free of late signal timing problems. Cycle stealing is directly permitted by the formulation. However, moderate restrictions may be necessary to ensure that the timing constraint graph is acyclic. Forcing the constraint graph to be acyclic allows a broad range of existing optimization algorithms to be easily extended to better optimize circuits with levelsensitive latches. We describe the extension of two such algorithms, both of which attempt to solve the problem of selecting parts from a library to minimize area subject to a cycle time constraint. 1 The critical path method and timingdriven design When a circuit must be designed to satisfy stringent timing constraints, we say that the design is timingdriven. Researchers have described a wide variety of timingdriven design problems: logic synthesis, retiming, transistor sizing, part selection, input ordering, and placement and routing. Despite the range and variety of these problems, each approach is derived from a common framework for representing and enforcing timing constraints: the Critical Path Method (CPM) [1]. The application of CPM and a related technique called PERT to digital circuits was first described by Kirkpatrick and Clark [2] and later by Hitchcock, Smith, and Cheng [3]. In this paper, circuits are represented by a graph in which directed arcs represent delays and nodes represent electrically equipotential regions. Two special nodes, the source and sink, group circuit inputs and outputs, respectively. The circuit computation time is obtained by making a single pass through the graph. Beginning with the source
A Generalized Minimum Dynamic Power and HighSpeed Design Methods for . . .
, 2004
"... We formulate a linear program (LP) to simultaneously minimize the dynamic power and overall delay of a CMOS circuit. To eliminate all glitches either without or with minimal number of delay buffers, a CMOS gate is assumed to have adjustable input to output delays for each input. Since these delays a ..."
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We formulate a linear program (LP) to simultaneously minimize the dynamic power and overall delay of a CMOS circuit. To eliminate all glitches either without or with minimal number of delay buffers, a CMOS gate is assumed to have adjustable input to output delays for each input. Since these delays are not independent, a transistor sizing problem would require very complex nonlinear optimization. We solve the problem in three steps. First, CMOS gates are analyzed to determine the realizable maximum differential input delay, ub, for the device technology being used. Second, an LP assumes the gate input and output delays as independent variables and determines them for all gates. This LP satisfies (1) glitch elimination conditions and the realizability constraint (ub) for all gates, and (2) the specified overall delay for the circuit. The total number of constraints in our LP is a linear function of the circuit size. Third, all gates are designed with the delays determined by the LP. As a sample result, using ub =10 when we designed the c1355 benchmark circuit specifying a large overall delay, a zero buffer design was obtained. It consumed 33 % power and had three times the overall delay as compared to an unoptimized design. When the overall delay was constrained not to increase, the lowpower design required 64 delay bu ers and consumed 37% power.