Results 1  10
of
11
Performance optimization of VLSI interconnect layout
 Integration, the VLSI Journal
, 1996
"... This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. ..."
Abstract

Cited by 117 (32 self)
 Add to MetaCart
(Show Context)
This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, nontree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.
Clock Distribution Networks in Synchronous Digital Integrated Circuits
 Proc. IEEE
, 2001
"... this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path ..."
Abstract

Cited by 82 (5 self)
 Add to MetaCart
this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path and the clock skew of that path are described in Section IV. The interplay among the aforementioned three subsystems making up a synchronous digital system is described in Section V; particularly, how the timing characteristics of the memory and logic elements constrain the design and synthesis of clock distribution networks. Different forms of clock distribution networks, such as buffered trees and Htrees, are discussed. The automated layout and synthesis of clock distribution networks are described in Section VI. Techniques for making clock distribution networks less sensitive to process parameter variations are discussed in Section VII. Localized scheduling of the clock delays is useful in optimizing the performance of highspeed synchronous circuits. The process for determining the optimal timing characteristics of a clock distribution network is reviewed in Section VIII. The application of clock distribution networks to highspeed circuits has existed for many years. The design of the clock distribution network of certain important VLSIbased systems has been described in the literature, and some examples of these circuits are described in Section IX. In an effort to provide some insight into future and evolving areas of research relevant to highperformance clock distribution networks, some potentially important topics for future research are discussed in Section X. Finally, a summary of this paper with some concluding remarks is provided in Section XI
An iterative gate sizing approach with accurate delay evaluation
 in Proc. ICCAD
, 1995
"... This paper introduces a new gate sizing approach with accurate delay evaluation. The approach solves gate sizing problems by iterating local sizing results from linear programming within small variable ranges of gate sizes. In each iterative step, variable ranges of gate sizes are updated accordin ..."
Abstract

Cited by 9 (1 self)
 Add to MetaCart
This paper introduces a new gate sizing approach with accurate delay evaluation. The approach solves gate sizing problems by iterating local sizing results from linear programming within small variable ranges of gate sizes. In each iterative step, variable ranges of gate sizes are updated according to the result from a previous step. Solutions with accurate delay evaluation which consider input signal slopes and separately evaluate rising and falling delays are obtained after several iterative steps. A speedup technique is used to pick out gates actually involved in each local sizing step so as to reduce CPU time. Experiments on sample circuits show that our approach can provide solutions with smaller circuit area than conventional approaches for the same circuit delay or provide solutions under tight delay constraints where conventional approaches can not reach. Moreover, our approach is faster than the conventional approaches for most circuits, especially under loose delay constraints. 1
Modeling and Optimization of VLSI Interconnects
, 1999
"... As very large scale integrated (VLSI) circuits move into the era of deepsubmicron (DSM) technology and gigahertz frequency, the system performance has increasingly become dominated by the interconnect delay. This dissertation presents five related research topics on interconnect layout optimizati ..."
Abstract

Cited by 6 (0 self)
 Add to MetaCart
As very large scale integrated (VLSI) circuits move into the era of deepsubmicron (DSM) technology and gigahertz frequency, the system performance has increasingly become dominated by the interconnect delay. This dissertation presents five related research topics on interconnect layout optimization, and interconnect extraction and modeling: the multisource wire sizing (MSWS) problem, the simultaneous transistor and interconnect sizing (STIS) problem, the global interconnect sizing and spacing (GISS) problem, the interconnect capacitance extraction problem, and the interconnect inductance extraction problems. Given a routing tree with multiple sources, the MSWS problem determines the optimal widths of the wire segments such that the delay is minimized. We reveal several interesting properties for the optimal MSWS solution, of which the most important is the bundled refinement property. Based on this property, we propose a polynomial time algorithm, which uses iterative bundled refinement operations to compute lower and upper bounds of an optimal solution. Since the algorithm often achieves identical lower and upper bounds in experiments, the optimal solution is obtained simply by the bound computation. Furthermore, this algorithm can be used for singlesource wire sizing problem and runs 100x xxi faster than previous methods. It has replaced previous singlesource wire sizing methods in practice.
Leakage poweraware clock skew scheduling: Converting stolen time into leakage power reduction
 in DAC
, 2008
"... Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is “stolen ” from fast combinational blocks to be used by slower blocks to meet a more stringent clock cycle time. Instead, we can leverage on the borrowed time to a ..."
Abstract

Cited by 3 (0 self)
 Add to MetaCart
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is “stolen ” from fast combinational blocks to be used by slower blocks to meet a more stringent clock cycle time. Instead, we can leverage on the borrowed time to achieve leakage power reduction during gate sizing and/or dual Vth assignment. In this paper, we present the first approach to the best of our knowledge for integrating clock skew scheduling, threshold voltage assignment, and gate sizing into one optimization formulation. Over 29 circuits in the ISCAS89 benchmark suite, this integrated approach can reduce leakage power by as much as 55.83 % and by 18.79 % on average, compared to using combinational circuit based power optimization on each combinational block without considering clock skews. Using a 65nm dual Vth technology library, this corresponds to a 23.87 % peak reduction (6.15 % on average) in total power at the ambient operating temperature. The average total power reduction further increases to 9.83 % if the high temperature library of the same process technology is used.
Optimization of critical paths in circuits with levelsensitive latches
 IN PROC. INT. CONF. COMPUTERAIDED DESIGN
, 1994
"... A simple extension of the critical path method is presented which allows more accurate optimization of circuits with levelsensitive latches. The extended formulation provides a sufficient set of constraints to ensure that, when all slacks are nonnegative, the corresponding circuit will be free of ..."
Abstract

Cited by 3 (0 self)
 Add to MetaCart
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with levelsensitive latches. The extended formulation provides a sufficient set of constraints to ensure that, when all slacks are nonnegative, the corresponding circuit will be free of late signal timing problems. Cycle stealing is directly permitted by the formulation. However, moderate restrictions may be necessary to ensure that the timing constraint graph is acyclic. Forcing the constraint graph to be acyclic allows a broad range of existing optimization algorithms to be easily extended to better optimize circuits with levelsensitive latches. We describe the extension of two such algorithms, both of which attempt to solve the problem of selecting parts from a library to minimize area subject to a cycle time constraint.
UsefulSkew Clock Routing With Gate Sizing for Low Power Design
"... Instead of zeroskew or assuming a xed skew bound, we seek to produce useful skews in clock routing. This is motivated by the fact that negative skewmay allow a larger timing budget for gate sizing. We construct a usefulskew tree (UST) such that the total clock and logic power(measured as a cost ..."
Abstract
 Add to MetaCart
(Show Context)
Instead of zeroskew or assuming a xed skew bound, we seek to produce useful skews in clock routing. This is motivated by the fact that negative skewmay allow a larger timing budget for gate sizing. We construct a usefulskew tree (UST) such that the total clock and logic power(measured as a cost function) is minimized. Given a required clock period and feasible gate sizes, a set of negative and positive skew bounds are generated. The allowable skews within these bounds and feasible gate sizes form the feasible solution space of our problem. We use a merging segment perturbation procedure and a simulated annealing approach to explore various tree congurations. This is complemented by a bipartitioning heuristic to generate appropriate connection topology and take advantage of useful skews. Experimental results have shown 11 % to 22 % total power reduction over previous methods of clock routing with zeroskew or single xed skew bound and separately sizing logic gates. 1
474 CLOCK DISTRIBUTION IN SYNCHRONOUS SYSTEMS CLOCK DISTRIBUTION IN SYNCHRONOUS SYSTEMS
"... In a synchronous digital system, the clock signal is used to define a time reference for the movement of data within that system. Because this function is vital to the operation of a synchronous system, much attention has been given to the characteristics of these clock signals and the networks used ..."
Abstract
 Add to MetaCart
In a synchronous digital system, the clock signal is used to define a time reference for the movement of data within that system. Because this function is vital to the operation of a synchronous system, much attention has been given to the characteristics of these clock signals and the networks used in their distribution. Clock signals are often regarded as simple control signals; however, these signals have some very special characteristics and attributes. Clock signals are typically loaded with the greatest fanout, travel over the greatest distances, and operate at the highest speeds of any signal, either control or data, within the entire system. Because the data signals are provided with a temporal reference by the clock signals, the clock waveforms must be particularly clean and sharp. Furthermore, these clock signals are particularly affected by technology scaling, in that long global interconnect
Clock Network Sizing in Presence of Power Supply Noise
"... In this paper, we present a novel sequential linear programming approach to the problem of clock network sizing. The original nonlinear programming problem is transformed to a sequence of linear programs, by taking the first order Taylor’s expansion of clock path delay with respect to buffer and wir ..."
Abstract
 Add to MetaCart
(Show Context)
In this paper, we present a novel sequential linear programming approach to the problem of clock network sizing. The original nonlinear programming problem is transformed to a sequence of linear programs, by taking the first order Taylor’s expansion of clock path delay with respect to buffer and wire widths. The sensitivities of clock path delay, with respect to buffer and wire widths, are efficiently updated for each linear program by applying time domain analysis to the clock network in a divideandconquer fashion. Our technique takes into account process variation and power supply noise, which have significant impacts on clock skew. We demonstrate experimentally that the proposed technique is not only capable of effectively optimizing clock skew and power consumption, but also able to provide more accurate delay and skew results compared to the traditional approach. 1.