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Performance optimization of VLSI interconnect layout
 Integration, the VLSI Journal
, 1996
"... This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. ..."
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Cited by 109 (32 self)
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This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, nontree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.
A new class of iterative Steiner tree heuristics with good performance
 IEEE TRANS. COMPUTERAIDED DESIGN
, 1992
"... ... problem is very important for such aspects of physical layout as global routing and wiring estimation. Virtually all previous heuristics for computing rectilinear Steiner trees begin with a minimum spanning tree (MST) topology and rearrange edges to induce Steiner points. This paper gives a more ..."
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Cited by 98 (32 self)
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... problem is very important for such aspects of physical layout as global routing and wiring estimation. Virtually all previous heuristics for computing rectilinear Steiner trees begin with a minimum spanning tree (MST) topology and rearrange edges to induce Steiner points. This paper gives a more direct approach which makes a significant departure from such spanning treebased strategies: we iteratively find optimal Steiner points to be added to the layout. Our method not only gives improved averagecase performance, but also escapes the worstcase examples of existing approaches. We show that the performance ratio of our method can never be as bad as 3/2, and is in fact bounded by 4/3 on the entire class of instances where the c(MST)/c(MRST) cost ratio is exactly 3/2. Sophisticated computational geometry techniques allow efficient and practical implementation, and the method is naturally suited to technological regimes where, e.g., via costs can be high and the number of Steiner points should be limited. Extensive performance results show a 2 % to 3 % wire length reduction over the best previous heuristics. We describe a number of variants and extensions, and suggest directions for further research.
Closing the Gap: NearOptimal Steiner Trees in Polynomial Time
 IEEE Trans. ComputerAided Design
, 1994
"... The minimum rectilinear Steiner tree (MRST) problem arises in global routing and wiring estimation, as well as in many other areas. The MRST problem is known to be NPhard, and the best performing MRST heuristic to date is the Iterated 1Steiner (I1S) method recently proposed by Kahng and Robins. In ..."
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Cited by 43 (13 self)
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The minimum rectilinear Steiner tree (MRST) problem arises in global routing and wiring estimation, as well as in many other areas. The MRST problem is known to be NPhard, and the best performing MRST heuristic to date is the Iterated 1Steiner (I1S) method recently proposed by Kahng and Robins. In this paper we develop a straightforward, efficient implementation of I1S, achieving a speedup factor of three orders of magnitude over previous implementations. We also give a parallel implementation that achieves nearlinear speedup on multiple processors. Several performanceimproving enhancements enable us to obtain Steiner trees with average cost within 0.25% of optimal, and our methods produce optimal solutions in up to 90% of the cases for typical nets. We generalize I1S and its variants to three dimensions, as well as to the case where all the pins lie on k parallel planes, which arises in, e.g., multilayer routing. Motivated by the goal of reducing the running times of our algorith...
LowDegree Minimum Spanning Trees
 Discrete Comput. Geom
, 1999
"... Motivated by practical VLSI routing applications, we study the maximum vertex degree of a minimum spanning tree (MST). We prove that under the Lp norm, the maximum vertex degree over all MSTs is equal to the Hadwiger number of the corresponding unit ball; we show an even tighter bound for MSTs where ..."
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Cited by 21 (1 self)
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Motivated by practical VLSI routing applications, we study the maximum vertex degree of a minimum spanning tree (MST). We prove that under the Lp norm, the maximum vertex degree over all MSTs is equal to the Hadwiger number of the corresponding unit ball; we show an even tighter bound for MSTs where the maximum degree is minimized. We give the bestknown bounds for the maximum MST degree for arbitrary Lp metrics in all dimensions, with a focus on the rectilinear metric in two and three dimensions. We show that for any finite set of points in the rectilinear plane there exists an MST with maximum degree of at most 4, and for threedimensional rectilinear space the maximum possible degree of a minimumdegree MST is either 13 or 14. 1 Introduction Minimum spanning tree (MST) construction is a classic optimization problem for which several efficient algorithms are known [9] [15] [19]. Solutions of many other problems hinge on the construction of an MST as an intermediary step [4], with th...
Steiner Tree Problems
, 2000
"... this article, we will review important developments in 1990s and discuss some open problems which may induce important developments in this centrary ..."
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Cited by 8 (4 self)
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this article, we will review important developments in 1990s and discuss some open problems which may induce important developments in this centrary
Minimum steiner tree construction
 IN ALPERT, C.J., MEHTA, D.P. AND SAPATNEKAR, S.S. (EDS), THE HANDBOOK OF ALGORITHMS FOR VLSI PHYSICAL DESIGN AUTOMATION
, 2009
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An efficient lowdegree RMST algorithm for VLSI/ULSI physical design
 in Lecture Notes in Computer Science (LNCS) 3254—Integrated Circuit and System Design
, 2004
"... Abstract. Motivated by very/ultra large scale integrated circuit (VLSI/ULSI) physical design applications, we study the construction of rectilinear minimum spanning tree (RMST) with its maximum vertex degree as the constraint. Given a collection of n points in the plane, we firstly construct a graph ..."
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Abstract. Motivated by very/ultra large scale integrated circuit (VLSI/ULSI) physical design applications, we study the construction of rectilinear minimum spanning tree (RMST) with its maximum vertex degree as the constraint. Given a collection of n points in the plane, we firstly construct a graph named the boundeddegree neighborhood graph (BNG). Based on this framework, we propose an O(n log n) algorithm to construct a 4BDRMST (RMST with maximum vertex degree ≤ 4). This is the first 4BDRMST algorithm with such a complexity, and experimental results show that the algorithm is significantly faster than the existing 4BDRMST algorithms. 1
A New Class of Steiner Tree Heuristics with Good Performance: the Iterated 1Steiner Approach
"... Virtually all previous methods for the rectilinear Steiner tree problem begin with a minimum spanning tree topology and rearrange edges to induce Steiner points. This paper gives a more direct approach: we iteratively find optimal Steiner points to be added to the layout. Our method gives improved a ..."
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Virtually all previous methods for the rectilinear Steiner tree problem begin with a minimum spanning tree topology and rearrange edges to induce Steiner points. This paper gives a more direct approach: we iteratively find optimal Steiner points to be added to the layout. Our method gives improved averagecase performance, and also escapes the worstcase examples of existing approaches. Sophisticated computational geometry techniques allow efficient and practical implementation, and the method is naturally suited to realworld VLSI regimes where, e.g., via costs can be high. Extensive performance results show almost 3 percent wirelength reduction over the best existing methods. We describe a number of variants and extensions, and suggest directions for further research. 1
Closing the Gap: NearOptimal Steiner Trees in Polynomial Time
"... We propose several efficient enhancements to the Iterated 1Steiner (I1S) heuristic of Kahng and Robins [17] for the minimum rectilinear Steiner tree problem. For typical nets, our methods obtain average performance of less than 0.25% from optimal, and produce optimal solutions up to 90% of the t ..."
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We propose several efficient enhancements to the Iterated 1Steiner (I1S) heuristic of Kahng and Robins [17] for the minimum rectilinear Steiner tree problem. For typical nets, our methods obtain average performance of less than 0.25% from optimal, and produce optimal solutions up to 90% of the time. We generalize I1S and its variants to three dimensions, as well as to the case where all the pins lie on k parallel planes, which arises in, e.g., multilayer routing. Our algorithms are highly parallelizable, and extend to arbitrary weighted graphs, and thus, our methods are applicable in practical routing regimes. We prove that given a pointset in the Manhattan plane, the minimum spanning tree (MST) degree of any specific point can be made to be 4 or less; similarly, we show that in three dimensions, the MST degree of any specific point can be made 14 or less. Using a perturbative argument, these results have been recently extended to show that for every pointset in the Manhatt...
On the Number of Minimal 1Steiner Trees
, 1994
"... We count the number of nonisomorphic geometric minimum spanning trees formed by ..."
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We count the number of nonisomorphic geometric minimum spanning trees formed by