This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, non-tree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.

... problem is very important for such aspects of physical layout as global routing and wiring estimation. Virtually all previous heuristics for computing rectilinear Steiner trees begin with a minimum spanning tree (MST) topology and rearrange edges to induce Steiner points. This paper gives a more direct approach which makes a significant departure from such spanning treebased strategies: we iteratively find optimal Steiner points to be added to the layout. Our method not only gives improved average-case performance, but also escapes the worst-case examples of existing approaches. We show that the performance ratio of our method can never be as bad as 3/2, and is in fact bounded by 4/3 on the entire class of instances where the c(MST)/c(MRST) cost ratio is exactly 3/2. Sophisticated computational geometry techniques allow efficient and practical implementation, and the method is naturally suited to technological regimes where, e.g., via costs can be high and the number of Steiner points should be limited. Extensive performance results show a 2 % to 3 % wire length reduction over the best previous heuristics. We describe a number of variants and extensions, and suggest directions for further research.

The minimum rectilinear Steiner tree (MRST) problem arises in global routing and wiring estimation, as well as in many other areas. The MRST problem is known to be NP-hard, and the best performing MRST heuristic to date is the Iterated 1-Steiner (I1S) method recently proposed by Kahng and Robins. In this paper we develop a straightforward, efficient implementation of I1S, achieving a speedup factor of three orders of magnitude over previous implementations. We also give a parallel implementation that achieves near-linear speedup on multiple processors. Several performance-improving enhancements enable us to obtain Steiner trees with average cost within 0.25% of optimal, and our methods produce optimal solutions in up to 90% of the cases for typical nets. We generalize I1S and its variants to three dimensions, as well as to the case where all the pins lie on k parallel planes, which arises in, e.g., multi-layer routing. Motivated by the goal of reducing the running times of our algorith...

Motivated by practical VLSI routing applications, we study the maximum vertex degree of a minimum spanning tree (MST). We prove that under the Lp norm, the maximum vertex degree over all MSTs is equal to the Hadwiger number of the corresponding unit ball; we show an even tighter bound for MSTs where the maximum degree is minimized. We give the best-known bounds for the maximum MST degree for arbitrary Lp metrics in all dimensions, with a focus on the rectilinear metric in two and three dimensions. We show that for any finite set of points in the rectilinear plane there exists an MST with maximum degree of at most 4, and for three-dimensional rectilinear space the maximum possible degree of a minimum-degree MST is either 13 or 14. 1 Introduction Minimum spanning tree (MST) construction is a classic optimization problem for which several efficient algorithms are known [9] [15] [19]. Solutions of many other problems hinge on the construction of an MST as an intermediary step [4], with th...

Motivated by practical VLSI applications, we study the maximum vertex degree in a minimum spanning tree (MST) under arbitrary L p metrics. We show that the maximum vertex degree in a maximum-degree L p MST equals the Hadwiger number of the corresponding unit ball. We then determine the maximum vertex degree in a minimum-degree L p MST; towards this end, we define the MST number, which is closely related to the Hadwiger number. We bound Hadwiger and MST numbers for arbitrary L p metrics, and focus on the L 1 metric, where little was known. We show that the MST number of a diamond is 4, and that for the octahedron the Hadwiger number is 18 and the MST number is either 13 or 14. We also give an exponential lower bound on the MST number for an L p unit ball. Implications to L p minimum spanning trees and related problems are explored.

The minimum rectilinear Steiner tree (MRST) problem arises in global routing and wiring estimation, as well as in many other areas. The MRST problem is known to be NPhard, and the best performing MRST heuristic to date is the Iterated 1-Steiner (I1S) method recently proposed by Kahng and Robins [13]. I1S achieves significantly improved averagecase performance while avoiding the worst-case examples from which other approaches suffer, yet the algorithm has heretofore lacked a practical implementation. In this paper we develop a straightforward, efficient implementation of I1S, achieving speedup factors of over 200 compared to previous implementations. We also propose a parallel implementation of I1S that achieves near-linear speedup on K processors. Extensive empirical testing confirms the viability of our approaches, which allow for the first time the benchmarking of I1S on nets containing several hundred pins. 1 Introduction The minimum rectilinear Steiner tree problem is c...

this article, we will review important developments in 1990s and discuss some open problems which may induce important developments in this centrary

Abstract. Motivated by very/ultra large scale integrated circuit (VLSI/ULSI) physical design applications, we study the construction of rectilinear minimum spanning tree (RMST) with its maximum vertex degree as the constraint. Given a collection of n points in the plane, we firstly construct a graph named the bounded-degree neighborhood graph (BNG). Based on this framework, we propose an O(n log n) algorithm to construct a 4-BDRMST (RMST with maximum vertex degree ≤ 4). This is the first 4-BDRMST algorithm with such a complexity, and experimental results show that the algorithm is significantly faster than the existing 4-BDRMST algorithms. 1

This paper concentrates on the Steiner Minimal Tree problem, henceforth referred to as the SMT problem. We present several algorithms for calculating Steiner Minimal Trees, including the first parallel algorithm for doing so. Several implementation issues are discussed, some new results are presented, and several ideas for future work are proposed.